Clevo P177SM Service Manual page 66

Schematic Diagrams
Processor 2/7
Sheet 3 of 60
Processor 2/7
34
Buffered reset to CPU
13,22,46
B - 4 Processor 2/7
Haswell Processor 2/7 ( MISC,JTAG,CLK )
24,34
44 H_PROCHOT#
24 H_THRMTRIP#
21 H_PM_SYNC
24 H_CPUPWRGD
24 PCH_PLTRST_CPU
CRB 0905
D01A_1018_Alex
D02_1105_Alex
H_PROCHOT#_R H_PROCHOT#_R
Gary D03 valueÅܧó0103
C123
D02_1116_Alex
H_PROCHOT#
Q26
G C390
H_PROCHOT#_EC
MTN7002ZHS3
47P_50V_NPO_04
R385
100K_04
CAD Note: Capacitor need to be placed
close to buffer output pin
3.3VS
R95 R51 75_04
1.05VS
10K_04
D CRB 0905
BUF_CPU_RST#
CRB 0906 R60 43.2_1%_04
2 G
PLT_RST#
S Q9A
D MTDN7002ZHS6R
5 G
S Q9B
MTDN7002ZHS6R R386 *1.5K_1%_04
R390 C439 R59
100K_04 68P_50V_NPO_04 *750_1%_04
U32B
SKTOCC# AP32 MISC
SKTOCC
AN32
H_CATERR#
CATERR
H_PECI AR27
R128 *10mil_short
H_PECI
PECI
FC_AK31 AK31
AM30 FC_AK31
H_PROCHOT# R380 56_1%_04 H_PROCHOT#_R
PROCHOT
H_THRMTRIP# H_THRMTRIP#_R AM35
R61 *10mil_short
THERMTRIP
R691 *1K_04 D01a_1009_Alex
1.05VS
H_PM_SY NC H_PM_SYNC_R AT28
R139 *10mil_short
PM_SY NC
H_CPUPWRGD H_CPUPWRGD_R AL34
R114 *10mil_short
AC10 PWRGOOD
PMSYS_PWRGD_BUF R409 0_04 VDDPWRGOOD_R
SM_DRAMPWROK
PCH_PLTRST_CPU CPU_RST# AT26
R692 0_04
PLTRSTIN
CRB 0905
BUF_CPU_RST# R700 *0_04
G28
R412 0_04 DPLL_REF_CLKN
27 CLK_DPNS_N DPLL_REF_CLKN
DPLL_REF_CLKP H28
R413 0_04
27 CLK_DPNS_P
DPLL_REF_CLKP
SSC_DPLL_REF_CLKN F27
R414 0_04
27 CLK_DP_N
SSC_DPLL_REF_CLKN
R415 0_04 SSC_DPLL_REF_CLKP E27
27 CLK_DP_P SSC_DPLL_REF_CLKP
D26
CLK_EXP_N
27 CLK_EXP_N BCLKN
CLK_EXP_P E26
27 CLK_EXP_P
BCLKP
SSC CLOCK TERMINATION STUFF
ONLY WHEN SSC CLOCK NOT USED
1u_6.3V_X5R_04
VCCIO_OUT
SSC_DPLL_REF_CLKP
R694 *10K_04
R696 *10K_04 SSC_DPLL_REF_CLKN
D01a_1009_Alex
R418 *100_04 H_THRMTRIP#
R693 *0_06 FC_AK31
1.05VS
C700 C701
S3 circuit:- DRAM PWR GOOD logic
3.3V 3.3V
C441
VDDQ
R423 R422
R427
1.82K_1%_04
1
21 PM_DRAM_PWRGD
4 PMSYS_PWRGD_BUF
2
R438
U31
*MC74VHC1G08DFT1G R426
*39_04
R421 0_04
Q54
G
13,39,41,42 SUSB
*MTN7002ZHS3
PU/PD for JTAG signals
Haswell rPGA EDS
XDP_TMS
R395 51_04
AP3 SM_RCOMP_0 XDP_TDI_R R400 51_04
SM_RCOMP_0 AR3
SM_RCOMP_1 XDP_PREQ# R397 *51_04
SM_RCOMP_1 AP2
SM_RCOMP_2 XDP_TDO_R R394 51_04
SM_RCOMP_2
AN3 CPUDRAMRST# XDP_TCLK
R405 51_04
SM_DRAMRST
XDP_TRST# R389 51_04
AR29
XDP_PRDY # XDP_TDO_R R404 *100_04
PRDY
AT29 XDP_PREQ#
PREQ
AM34 XDP_TCLK
TCK
AN33 XDP_TMS
TMS AM33
XDP_TRST#
TRST
AM31 XDP_TDI_R
TDI
AL33 XDP_TDO_R XDP_DBR_R
1K_04 R379
TDO AP33
XDP_DBR_R
DBR
AR30 XDP_BPM0
BPM_N_0
AN31 XDP_BPM1
DDR3 Compensation Signals
BPM_N_1 AN29
XDP_BPM2
BPM_N_2
AP31 XDP_BPM3
BPM_N_3
AP30 XDP_BPM4
BPM_N_4
AN28 XDP_BPM5 SM_RCOMP_0 R434 100_1%_04
BPM_N_5
AP29
XDP_BPM6
BPM_N_6
AP28 XDP_BPM7 SM_RCOMP_1
R425 75_1%_04
BPM_N_7
2 OF 9 SM_RCOMP_2 R433 100_1%_04
Processor Pullups/Pull downs
H_PROCHOT#
62_04
D01A_1018_Alex
H_CPUPWRGD_R 10K_1%_04
C108 *0.1u_16V_Y 5V_04
TRACE WIDTH 10MIL, LENGTH <500MILS
S3 circuit:- DRAM_RST# to memory
should be high during S3
VDDQ
R435 *0_04 R436
1K_04
BSS138 ( VGS 1.5V )
Q41
MTN7002ZHS3
CPUDRAMRST# S D
R441 1K_04
R432
DDR3_DRAMRST# 9,10,11,12
4.99K_1%_04
DRAMRST_CNTRL 4,20
C440
0.047u_10V_X7R_04
VDD3 13,19,20,21,23,24,25,26,27,29,34,36,37,40,41,42,45,46
3.3VS 5,9,10,11,12,13,14,16,17,18,19,20,21,22,24,25,26,27,28,29,30,32,33,34,35,36,37,41,44,46,61,62
3.3V 2,14,15,19,29,30,32,36,37,39,41,42,62
VDDQ 4,6,9,10,11,12,30,39
1.05VS 6,25,26,30,42,44,62
R402
VCCIO_OUT 5,6,44
*100K_04
1.05VS
3.3VS
VCCIO_OUT
R381
R113