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Schematic Diagrams

TPM

SLB9635TT & SLB9655TT Co-Layout
21
PM_CLKRUN#
Sheet 45 of 60
TPM
B - 46 TPM
LPC_AD0
20,30,34
LPC_AD0
LPC_AD1
20,30,34
LPC_AD1
LPC_AD2
20,30,34
LPC_AD2
LPC_AD3
20,30,34
LPC_AD3
PCLK_TPM
27
PCLK_TPM
SLB9655
LPC_FRAME#
20,30,34
LPC_FRAME#
PLT_RST#
¤£¤W¥ó
3,13,22
PLT_RST#
20,30,34
SERIRQ
PM_CLKRUN#
R324
*0_04
R296
*0_04
21
SUS_STAT#
TPM_BADD
3.3VS
TPM_PP
R188
*10K_04
SLB9655
¤£¤W¥ó
R322
*0_04
SLB9655
¤£¤W¥ó
Asserted before entering S3
LPC reset timing:
LPCPD# inactive to LRST# inactive 32~96us
HI: ACCESS
TPM _PP
LOW: NORM AL ( Internal PD )
HI: 4E/ 4F H
TPM _BADD
LOW: 2E/ 2F H
13,19,20,21,23,24,25,26,27,29,34,36,37,40,41,42,45
3,5,9,10,11,12,13,14,16,17,18,19,20,21,22,24,25,26,27,28,29,30,32,33,34,35,36,37,41,44,61,62
12/06 DVT¤£¤W¥ó Gary
SLB9635,SLB9655
¤W¥ó
U13
26
10
R315
*0_04
LAD0
VDD1
23
19
LAD1
VDD2
20
24
C181
LAD2
VDD3
17
LAD3
SLB9655
R107
*0.1u_16V_Y5V_04
21
TPM
¤W¥ó
*0_04
LCLK
12/06 DVT¤£¤W¥ó Gary
22
5
LFRAME#
VSB
16
R108
LRESET#
27
SERIRQ
15
D02_1112_Alex
CLKRUN#
28
6
LPCPD#
GPIO
2
GPIO2
9
TESTBI/BADD
13
XTALI
7
PP
14
D02A DEL X2,C187,C185,R317,R318
XTALO
1
NC_1
3
4
NC_2
GND_1
12
11
NC_3
GND_2
18
GND_3
8
25
TESTI
GND_4
*SLB9655TT
12/06 DVT¤£¤W¥ó Gary
SLB9655
¤W¥ó
12/06 DVT¤£¤W¥ó Gary
PLT_RST#
R325
*0_04
PCLK_TPM
R187
*33_04
TPM_PP
R158
*10K_04
TPM_BADD
R156
*10K_04
12/06 DVT¤£¤W¥ó Gary
R157
*10K_04
VDD3
3.3VS
3.3VS
12/06 DVT¤£¤W¥ó Gary
C171
C205
C213
*0.1u_16V_Y 5V_04
*0.1u_16V_Y 5V_04
*1u_6.3V_X5R_04
VDD3
*0_04
SLB9635
C186
¤W¥ó
*0.1u_16V_Y5V_04
12/06 DVT¤£¤W¥ó Gary
Gary 10/17(Fix X'tal¤£¤W¥óby ¦@¥Î½u¸ô)
TPM_BADD
C217
*10p_50V_04
3.3VS

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