Supermicro X11DGQ User Manual page 38

Super X11DGQ User's Manual
DCPMM Memory Population Tables for 2nd Gen Intel Xeon Scalable-SP
Processors
Note: Only 2nd Gen Intel Xeon Scalable-SP (82xx/62xx/52xx/4215 series) processors
support DCPMM memory.
Modes P1-DIMMF1
AD
DCPMM
MM
DCPMM
AD + MM DCPMM
DRAM1
DRAM2
DRAM3
Note: DDR4 single rank x8 is not available for DCPMM Memory Mode or App-Direct Mode.
DCPMM
•
Mode definitions: AD=App Direct Mode, MM=Memory Mode, AD+MM=Mixed Mode
•
For MM, general DDR4+DCPMM ratio is between 1:4 and 1:16. Excessive capacity for DCPMM can be used for AD.
•
For each individual population, rearrangements between channels are allowed as long as the resulting population is
compliant with the X11 memory population rules for the 2nd Gen Intel Xeon Scalable-SP processors.
•
For each individual population, please use the same DDR4 DIMM in all slots.
•
For each individual population, sockets are normally symmetric with exceptions for 1 DCPMM per socket and 1 DCPMM
per node case. Currently, DCPMM modules operate at 2666 MHz.
•
No mixing of DCPMM and NVMDIMMs within the same platform is allowed.
•
This DCPMM population guide targets a balanced DCPMM-to-DRAM-cache ratio in MM and MM + AD modes.
DIMM Type
RDIMM
LRDIMM
LRDIMM 3DS
Symmetric Population within 1 CPU Socket
P1-DIMME1 P1-DIMMD1 P1-DIMMA1
DRAM1 DRAM1 DRAM1
DRAM1 DRAM1 DRAM1
DRAM3 DRAM3 DRAM3
Legend
(for the two tables above)
DDR4 Type
RDIMM 3DS RDIMM LRDIMM
RDIMM -
RDIMM 3DS RDIMM LRDIMM
Legend
(for the first two tables above)
Capacity
Any Capacity (Uniformly for all channels for a given configuration)
Validation Matrix (DDR4 DIMMs Validated w/DCPMM)
Ranks Per DIMM
& Data Width
(Stack)
1Rx4
2Rx8
2Rx4
4Rx4
8Rx4 (4H)
38
P1-DIMMB1 P1-DIMMC1
DRAM1 DCPMM
DRAM1
DCPMM
DRAM3 DCPMM
Capacity
3DS LRDIMM
Refer to Validation Matrix
(DDR4 DIMMs validated with
-
DCPMM) below.
-
DIMM Capacity (GB)
DRAM Density
4Gb
8GB
8GB
16GB
N/A
N/A
Channel Config.
1-1-1
1-1-1
1-1-1
8Gb
16GB
16GB
32GB
64GB
128GB