Read/Write Register In Batch Mode (Burst) - CMOSTEK CMT2310A Manual

For 3-wire based register reading operation, both MCU and CMT2310A will have to switch the direction of their IO (SDIO)
between the address bit 0 and the data bit 7, that is, the CMT2310A should switch from input to output, while the MCU from output
to input. As shown in the above figure, please notice the dot line in the middle, here strongly suggest that the MCU switches the
IO to input mode before sending out the falling edge of the SCLK; as for CMT2310A, it should switch the IO to output mode after it
has gotten the falling edge of the SCLK. This can avoid the possible electrical conflict caused by both of them setting SDIO as
output. For MCU, this kind of problems may cause reset or other abnormal behaviors.

5.1.2 Read/Write Register in Batch Mode (BURST)

Besides the single-byte based register read/write stated above, SPI can also support Burst based register read/write. The
BURST read/write operation is triggered by writing to the address BRW_PORT of Page 0x7B. When the r/w bit is 0, the register
will be written, while as it was 1, the register will be read.
The BURST read/write can also be performed via 3-wire SPI. When 3-wire is used, outputting read data and inputting write data
are both performed on the SDI pin. When using 4-wire, write data is input from SDI, and read data is output from SDO. The
operation flow of the BURST read/ write is that: accessing the FIFO operation port at the address 0x7B first (the write/read bit
inside determines whether it is a read or write operation), then followed by a stage of data reading/writing all along until users
determine to complete the operation.
Figure 13. SPI (4-wire) BURST Read Register Timing
Figure 14. SPI (4-wire) BURST Write Register Timing
Figure 15. SPI (3-wire) BURST Read Register Timing
Rev 1.0E | Page25/50
CMT2310A
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