Fifo Read Operation - CMOSTEK CMT2310A Manual

5.2.1 FIFO Read Operation

To access FIFO, the MCU should first configure a few registers to set up the FIFO read/write mode, as well as some other
operating modes. As shown in the figure below, it is the read and write timing in determined operating mode. FIFO operation is
triggered by writing into address 0x7A in Page 0, it will trigger write operation when r/w bit is 0 and trigger read operation when
r/w bit is 1.
FIFO read/writer operations can also be done through 3-wire SPI. In 3-wire SPI case, read data output and write data input are all
fulfilled on SDI pin, while in 4-wire SPI case write data is input on SDI, and read data is output on SDO. The procedure of FIFO is:
access address of 0x7A first, namely the FIFO operation port with the r/w bit determining whether it is read or writer operation;
then continue reading or writing data, and when to finish is determined by users.
Figure 17. SPI (4-wire) Read FIFO Timing
Figure 18. SPI (4-wire) Write FIFO Timing
Figure 19. SPI (3-wire) Read FIFO Timing
Rev 1.0E | Page27/50
CMT2310A
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