Function Description - CMOSTEK CMT2310A Manual

CMT2310A

4 Function Description

The CMT2310A is a high integrated mixed-signal transceiver, which employs a 32 MHz crystal to provide PLL reference
frequency and digital clock with supporting of OOK, 2-(G)FSK, 4 (G)FSK modulation/demodulation as well as Direct and Packet
Data processing modes.
Figure 4. Functional Block Diagram
In receiver part, the chip applies LNA+MXR+PGA+ADC+PLL low-IF architecture to achieve the Sub-GHz wireless receiving
function. In transmitter part, it applies PLL+PA architecture to achieve the Sub-1 GHz wireless transmitting function. The chip can
achieve high-performance RF transmission and receiving with no need of extra RF switch components,
In the receiver system, the analog circuit mixes the RF signal to IF and converts the signal from analog to digital through ADC
module, then outputs the two signal paths I/Q to the digital circuit for digital demodulation.The digital circuit is responsible for
mixing the IF signal to zero-frequency (baseband) and performing a series of filtering and decision processing, meanwhile it
applies AFC and AGC to control the analog circuit dynamically, and finally the original signal is demodulated. After demodulation,
the signal is sent to the decoder for decoding and then filled into FIFO, or output to GPIO directly.
In the transmitter system, the digital circuit encodes and packets the data then sends it to the modulator (or send data directly to
modulator without encoding). Then modulator will directly control the PLL and PA to have 2 (G)FSK, 4 (G)FSK or OOK based
modulation then transmit out the data.
The chip integrates a mini micro-controller (supporting supplier internal programming only), which controls and schedules various
functions and operations like auto-ACK, auto-frequency-hopping, DUTY-CYCLE based low-power Tx and Rx, CSMA function,
etc.
The chip provides SPI communication port. The external MCU can access registers to have various function configures, to
control the chip or access FIFO.
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