Transmitter; Receiver; Additional Functions; Power-On Reset (Por) - CMOSTEK CMT2310A Manual

CMT2310A

4.1 Transmitter

The transmitter of CMT2310A is based on direct frequency synthesis technology. Its carrier is generated by a low-noise
fractional-N frequency synthesizer. The modulated data is transmitted by an efficient single-ended power amplifier(PA).The output
power can be read and written via the register, with configurable value ranging from -10 dBm to +20 dBm by a step of 1 dB.
In OOK mode, when PA switches on and off quickly according to data transmitted, it will easily produce spectral spurs and
glitches near the target carrier. Through the PA Ramping mechanism, it can help to minimize the spurs and glitches. In FSK
mode, the transmitter supports to have Gaussian filtering on signals before transmission, namely GFSK, thus to make the
transmitting spectrum more concentrated.
Users can design a PA matching network based on specific application requirements to optimize the transmission efficiency at
the required output power. Typical application schematics and required BOMs are detailed in Section 3 Typical Application
Schematic.
The transmitter can work in direct mode and packet mode respectively. In direct mode, data is sent to the chip directly through the
DIN pin of the chip then transmitted directly. In packet mode, data can be pre-loaded into the FIFO in STBY status and then
transmitted along with other packet elements. In 4FSK mode, it only supports data transmitting from FIFO.

4.2 Receiver

An ultra-low-power, high-performance low-IF OOK/ FSK receiver is built in the CMT2310A. Its processing steps are as follows: 1)
the RF signal sensed by the antenna is amplified by the low-noise amplifier; 2) the signal is down-converted to the intermediate
frequency by the quadrature mixer; 3) the signal is further amplified by the programmable amplifier; 4) The signal is sent to the
digital domain through A/D convertor for digital demodulation processing. During power on reset (POR), each analog module is
calibrated to the internal reference voltage. This allows the chip to keep its best performance at different temperatures and
voltages. Baseband filtering and demodulation is accomplished by the digital demodulator. The AGC loop adjusts the system
gain to optimize the performance parameters such as system linearity, selectivity and sensitivity.
Leveraging CMOSTEK's low-power design technology, the receiver in always-on mode consumes only a very low power.The
periodic operating mode and wake-up function can further reduce the average power consumption of the system to satisfy
applications with strict power consumption requirements.
Similar to the transmitter, the CMT2310A receiver can operate in direct mode and packet mode as well.In direct mode, the
demodulator output data can be directly output through the DOUT pin of the chip. DOUT can be assigned to GPIO by
configuration. In packet mode, the demodulator data output is sent to the data packet handler, get decoded then is filled into the
FIFO, then MCU can read the FIFO through SPI interface.

4.3 Additional Functions

4.3.1 Power-On Reset (POR)

The power-on reset circuit detects the change of the VDD power supply and generate reset signal to reset the entire CMT2310A
system. After the POR, the MCU must go through initialization process and re-configure the CMT2310A. There are two situations
that will lead to the generation of POR.
The first situation is a very short and sudden decrease of VDD. The corresponding POR triggering condition is that VDD
dramatically decreases by 0.9 V +/- 20% (namely 0.72 V – 1.08 V) within less than 2 us. To be noticed, it detects a decreasing
amplitude of the VDD but not the absolute value of VDD as shown in the figure below.
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