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ESD ECS-CPCIs/FPGA Hardware Manual

Compactpci serial to ethercat slave interface
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ECS-CPCIs/FPGA
®
CompactPCI Serial
to
®
EtherCAT
Slave Interface
Hardware Manual
to Products E.1108.02
ECS-CPCIs/FPGA
Hardware Manual Doc.-Nr.: E.1108.21 /-Rev 1.0
Page 1 of 28
esd electronics gmbh
Vahrenwalder Str. 207 • 30165 Hannover • Germany
http://www.esd.eu
Phone: +49 (0) 511 3 72 98-0 • Fax: +49 (0) 511 3 72 98-68

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Summary of Contents for ESD ECS-CPCIs/FPGA

  • Page 1 Products E.1108.02 ECS-CPCIs/FPGA Hardware Manual Doc.-Nr.: E.1108.21 /-Rev 1.0 Page 1 of 28 esd electronics gmbh Vahrenwalder Str. 207 • 30165 Hannover • Germany http://www.esd.eu Phone: +49 (0) 511 3 72 98-0 • Fax: +49 (0) 511 3 72 98-68...
  • Page 2 design.
  • Page 3 The changes in the document listed below affect changes in the hardware as well as changes in the description of the facts, only. Rev. Chapter Changes versus previous version Date First English manual 2022-03-04 Technical details are subject to change without further notice. ECS-CPCIs/FPGA Hardware Manual Doc.-Nr.: E.1108.21/ 1.0 Page 3 of 28...
  • Page 4 This NOTICE statement contains the general mandatory sign and gives information that must be heeded and complied with for a safe use. INFORMATION INFORMATION Notes to point out something important or useful. Page 4 of 28 Hardware Manual Doc.-Nr.: E.1108.21 /Rev. 1.0 ECS-CPCIs/FPGA...

  • Page 5: Safety Instructions

    ● The ECS-CPCIs/FPGA may become warm during normal use. Always allow adequate ventilation around the ECS-CPCIs/FPGA and use care when handling. ● Do not operate the ECS-CPCIs/FPGA adjacent to heat sources and do not expose it to unnecessary thermal radiation. Ensure an ambient temperature as specified in the technical data.
  • Page 6 It is the responsibility of the device's user to take care that necessary safety precautions for the...

  • Page 7: Table Of Contents

    5.1 Connector Assignment RJ45 ....................24 5.2 P3 – 96-Pin Header configured for LVTTL I/O ................. 25 5.3 JTAG FPGA (X1300) ......................26 6 Declaration of Conformity ....................... 27 7 Order Information ........................... 28 ECS-CPCIs/FPGA Hardware Manual Doc.-Nr.: E.1108.21/ 1.0 Page 7 of 28...
  • Page 8 Figure 3: Installing ESI to EtherCAT Workbench (picture detail) ..........12 Figure 4: Scan result showing “Slave 1 (ECS-CPCIs/FPGA)”, (picture detail) ......12 Figure 5: Process data view with “Slave 1 (ECS-CPCIs/FPGA)”, (picture detail) ......13 Figure 6: Block circuit diagram ..................... 14 Figure 7: PCB top view of ECS-CPCIs/FPGA ................

  • Page 9: Quick Start

    * Demo version of the EtherCAT Workbench and full version of the EtherCAT Stack object for Windows and Linux are included in delivery of ECS-CPCIs/FPGA. Drivers are also available for the real-time operating system QNX, others on request. The stack is also offered as source for own developments.

  • Page 10: Driver Installation

    64-bit Windows) and click Next: Figure 2: Update Driver Software 1.3.2 Linux The Linux driver for the esd EtherCAT slave device (ECS-CPCIs/FPGA) is usually delivered as source code. Please refer to “.../driver/ECS-.../linux/README” from the extracted Slave Stack Linux archive.

  • Page 11: Qnx

    The QNX EtherCAT slave driver is implemented as a resource manager and can be started easily. "use devecs-XXX" (XXX = board name) provides the call syntax of the driver, e.g. for an ECS- PCIe/FPGA board: # use devecs-pexesc devecs-pexesc - EtherCAT Slave Driver for esd PCIe boards devecs-pexesc [options] Options: -v[v...] Verbose level...

  • Page 12: Testing The Sample App. With The Workbench

    After the Workbench was (re)started a slave scan can be performed. Use the Online button to let the Workbench connect to its included Master and click the Scan button then: Figure 4: Scan result showing “Slave 1 (ECS-CPCIs/FPGA)”, (picture detail) INFORMATION These samples show your ECS-CPCIs/FPGA described as “Slave 1 (ECS-..)”,...

  • Page 13: Further Steps

    Figure 5: Process data view with “Slave 1 (ECS-CPCIs/FPGA)”, (picture detail) Double click the output (“Slave 1 (ECS-CPCIs/FPGA).RxPDO1.Output1”) to write a new value to the slave. The Slave sample application shows the new value in its console output, for example: “[Application] *** output1 changed to 1234”...

  • Page 14: Overview

    The FPGA contains Bus Master DMA Support to offload the CPU from copying the output process image data into the host memory. This is utilized by the esd EtherCAT Slave Stack. The ECS-CPCIs/FPGA can be easily configured by esd's EtherCAT Master or other masters. A Sample EtherCAT Slave Information File (ESI file in XML format) is provided.

  • Page 15: Pcb View With Connectors

    Overview 2.2 PCB View with Connectors Figure 7: PCB top view of ECS-CPCIs/FPGA NOTICE Read chapter “Hardware Installation” on page 18, before you start with the installation of the hardware! See also page 24 for signal assignment of the connectors.

  • Page 16: Leds

    Overview 2.3 LEDs 2.3.1 Position of the LEDs Figure 8: Connectors and LEDs of ECS-CPCIs/FPGA 2.3.2 LED Indication Indicator states Description blinking LED blinking cycle: 200 ms on, 200 ms off. flickering LED blinking cycle: 50 ms on, 50 ms off.

  • Page 17: Status Leds

    Overview 2.3.2.1 Status LEDs Four status LEDs are equipped in the front panel ECS-CPCIs/FPGA U1, U2, RUN, and ERROR. Indicator LED name in Function Colour Description schematic State diagram User LED1 yellow user defined via FPGA and driver LED800A User LED2...

  • Page 18: Hardware Installation

    Switch off your system and all connected peripheral devices (monitor, printer, etc.). Discharge your body as described above. Disconnect the system from the mains. Make sure that no risk arises from the system into which the ECS-CPCIs/FPGA shall be inserted. DANGER...

  • Page 19: Technical Data

    160 mm x 100 mm x 20 mm according to CPCI-S0 R1.0 Specification) Front panel: 3U/4HP compliant to IEEE 1101 Weight Ca. 160 g Table 4: General data of the module ECS-CPCIs/FPGA Hardware Manual Doc.-Nr.: E.1108.21/ 1.0 Page 19 of 28...

  • Page 20: Hardware Components

    The FPGA is identical to the PCIe EtherCAT Slave Card Author / Beckhoff Automation GmbH & Co. KG license holder Delivery Binary, installed in the unit at the factory License terms Beckhoff IP core licence Table 6: FPGA Page 20 of 28 Hardware Manual Doc.-Nr.: E.1108.21 /Rev. 1.0 ECS-CPCIs/FPGA...

  • Page 21: Ethercat Interface

    On customer request the lines can be modified as two differential 2,5V LVDS pairs (one sync and one latch function must be shifted to user I/O lines then). Ask our sales team (sales@esd.eu) for further information. Controller Integrated in FPGA...

  • Page 22: Pci Express Interface

    The serial number is read and distributed by the software driver. distribution Hardware ID The hardware ID is readable via a FPGA register. See “EtherCAT Slave Stack” manual for further information distribution Table 13: Hardware ID and serial number Page 22 of 28 Hardware Manual Doc.-Nr.: E.1108.21 /Rev. 1.0 ECS-CPCIs/FPGA...

  • Page 23: Software Support

    The FPGA contains Bus Master DMA Support to offload the CPU from copying the output process image data into the host memory. This is utilized by the esd EtherCAT Slave Stack. The Stack and the included complex sample application with sample ESI is tested against the EtherCAT CTT (default test set).

  • Page 24: Connector Assignments

    Permissible cable types: Cables of category 5 or higher must be used to grant the function in networks with up to 100 Mbits/s. esd grants the EC conformity of the product if the wiring is carried out with shielded twisted pair cables.

  • Page 25: P3 - 96-Pin Header Configured For Lvttl I/O

    GPIO signals (x = 0 - 15), see “EtherCAT Slave Manual”, chapter: 2.4.24 essIoctl(). (…) … Signal connected to FPGA pin (shown in brackets). Sync0/1 / Latch0/1… Sync, Latch signals from Distributed Clock Reserved (Latch0/1 / SYNC0/1) These signals are reserved for customizations. ECS-CPCIs/FPGA Hardware Manual Doc.-Nr.: E.1108.21/ 1.0 Page 25 of 28...

  • Page 26: Jtag Fpga (X1300)

    Connector Assignments 5.3 JTAG FPGA (X1300) See Figure 7: PCB top view of ECS-CPCIs/FPGA on page 15 for the position of the pins. Signal Direction Input Output Input Input Page 26 of 28 Hardware Manual Doc.-Nr.: E.1108.21 /Rev. 1.0 ECS-CPCIs/FPGA...

  • Page 27: Declaration Of Conformity

    Declaration of Conformity 6 Declaration of Conformity ECS-CPCIs/FPGA Hardware Manual Doc.-Nr.: E.1108.21/ 1.0 Page 27 of 28...

  • Page 28: Order Information

    P.4520.21 Table 15: Available manuals Printed Manuals If you need a printout of the manual additionally, please contact our sales team (sales@esd.eu) for a quotation. Printed manuals may be ordered for a fee. Page 28 of 28 Hardware Manual Doc.-Nr.: E.1108.21 /Rev. 1.0...

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