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XMC-CPU/T10
TM
XMC/PMC 64-bit PowerPC
T1022
Processor Board with FPGA
Hardware Manual
to Product V.2030.01
XMC-CPU/T10
Hardware Manual • Doc. No.: V.2030.21 / Rev. 1.2
Page 1 of 41
esd electronics gmbh
Vahrenwalder Str. 207 • 30165 Hannover • Germany
http://www.esd.eu
Phone: +49 (0) 511 3 72 98-0 • Fax: +49 (0) 511 3 72 98-68
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Related Manuals for ESD XMC-CPU/T10
Summary of Contents for ESD XMC-CPU/T10
- Page 1 XMC-CPU/T10 Hardware Manual • Doc. No.: V.2030.21 / Rev. 1.2 Page 1 of 41 esd electronics gmbh Vahrenwalder Str. 207 • 30165 Hannover • Germany http://www.esd.eu Phone: +49 (0) 511 3 72 98-0 • Fax: +49 (0) 511 3 72 98-68...
- Page 2 design.
- Page 3 2016-12-07 Chapter restructured and description of Ethernet LEDs added 2019-10-18 Description of VCCO13, VCCO34 and VCCO35 corrected Technical details are subject to change without further notice. XMC-CPU/T10 Hardware Manual • Doc. No.: V.2030.21 / Rev. 1.2 Page 3 of 41...
- Page 4 This NOTICE statement contains the general mandatory sign and gives information that must be heeded and complied with for a safe use. INFORMATION INFORMATION Notes to point out something important or useful. Page 4 of 41 Hardware Manual • Doc. No.: V.2030.21 / Rev. 1.2 XMC-CPU/T10...
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Page 5: Safety Instructions
It is the responsibility of the device's user to take care that necessary safety precautions for the device's network interface are in place. - Page 6 T1022 Processor Board with FPGA. The guarantee given by esd does not cover damages which result from improper use, usage not in accordance with regulations or disregard of safety instructions and warnings. ● The XMC-CPU/T10 is intended for installation on a base board according to IEEE 1386.1-2001 (PMC) or Vita 42.3 (XMC).
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Page 7: Table Of Contents
Debug Interface X400 and JTAG FPGA Interface X1900.............35 7.8.1 XMC-CPU-ADAPTER-FPGA ..................35 Description of the Units......................36 8.1 CPU............................. 36 8.1.1 Access Addresses from CPU to FPGA ...............36 8.2 FPGA........................... 37 XMC-CPU/T10 Hardware Manual • Doc. No.: V.2030.21 / Rev. 1.2 Page 7 of 41... - Page 8 8.2.1 GPIO Modules......................37 9. Bootloader..........................38 9.1 License..........................38 Configuration and Console Access..................38 Special Commands......................39 Order Information........................40 Page 8 of 41 Hardware Manual • Doc. No.: V.2030.21 / Rev. 1.2 XMC-CPU/T10...
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Page 9: Overview
16 Mbyte SPI Flash for boot loader and 32 Kbit I²C EEPROM for U-Boot environment offer non- volatile memory spaces. The XMC-CPU/T10 features a second 16 Mbyte 'fallback' SPI Flash, used for system recovery if a system crash occurs during a firmware update. Alternatively it can be used for application software. - Page 10 Up to 2 GByte DDR3 RAM is available. PMC only The XMC-CPU/T10 can be produced without the connectors P5 and P6 if the space on the carrier is limited. All these options are available for customized serial production in reasonable quantities.
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Page 11: Pcb With Connectors
See also page 25 and following for signal assignments of the connectors. The JTAG connectors and the Debug-interface connector have to be connected on the PCB bottom side of XMC-CPU/T10 (see Figure 3 for the position of the connectors and pins). XMC-CPU/T10 Hardware Manual •... -
Page 12: Pcb Bottom Layer View With Led And Coding Switches
XMC-CPU/T10. See also page 25 and following for signal assignments of the connectors. esd offers special adapters as accessories, see “Order Information” on page 40. The coding switches are described on page 15. Page 12 of 41 Hardware Manual •... -
Page 13: Leds
Ethernet bit rate: 10/100/1000 Mbit/s Ethernet activity on ETHx ACTx green Activity Flickering (reception and transmission of Ethernet data) (x... 0, 1) Table 2: Ethernet LEDs Activity and Link XMC-CPU/T10 Hardware Manual • Doc. No.: V.2030.21 / Rev. 1.2 Page 13 of 41... -
Page 14: Con Activity (Led 1222) And Usb Pwr (Led1230)
LEDs 3.2 CON Activity (LED 1222) and USB PWR (LED1230) The LEDs CON Activity and USB PWR are equipped on the rear side of the XMC-CPU/T10, see Figure 3 page 12. LED name Colour Indication Description (LED on) in schematic... -
Page 15: Hardware Configuration
LC_IO22 User GPIO for user configuration SW901 LC_IO21 LC_IO20 LC_IO15 LC_IO14 User GPIO for user configuration SW900 LC_IO13 LC_IO12 Table 4: Coding Switch SW2000, SW901, SW900 XMC-CPU/T10 Hardware Manual • Doc. No.: V.2030.21 / Rev. 1.2 Page 15 of 41... -
Page 16: Hardware Installation
Pay attention that the XMC-CPU/T10 is correctly installed on the carrier board. Fix the XMC-CPU/T10 with the screws on the carrier board. Use the four M 2.5 x 6 mm screws which are contained in the product package of the module. - Page 17 Hardware Installation Connect the Ethernet and the USB interfaces via the connectors in the front panel of the XMC-CPU/T10. 10. Connect the system to mains again (mains connector or safety fuse). 11. Switch on the system and the peripheral devices.
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Page 18: Technical Data
0% ... 90%, non-condensing Dimensions 149 mm x 74 mm x 10 mm Weight ca. 150 g with heat sink Table 5: General data of the module Page 18 of 41 Hardware Manual • Doc. No.: V.2030.21 / Rev. 1.2 XMC-CPU/T10... -
Page 19: Cpu And Memory
Port 1: RS232 Software Standard operating system drivers Port 0: miniUSB Type B Connectors Port 1: via P4 (PMC) Table 8: Data of the Ethernet interfaces XMC-CPU/T10 Hardware Manual • Doc. No.: V.2030.21 / Rev. 1.2 Page 19 of 41... -
Page 20: I²C Interface
The FT232R chip is bus powered. Electrical isolation Via digital isolator Connector Mini USB type-B socket in the front panel (CON) Table 11: Data of the USB Device interface CON Page 20 of 41 Hardware Manual • Doc. No.: V.2030.21 / Rev. 1.2 XMC-CPU/T10... -
Page 21: Pmc Interface
Alternative Signal Names in chapter “PMC P4 I/O Connector”, from page 29 and Xilinx documentation. Protection circuit None, current-limiting resistors are not provided. Connector XMC-P4 Table 14: Data of the digital in-/outputs via P4 XMC-CPU/T10 Hardware Manual • Doc. No.: V.2030.21 / Rev. 1.2 Page 21 of 41... -
Page 22: Digital In-/Outputs P6
+/-5 ppm at T = 25 °C (< 13 s/month) Buffer Goldcap, C = 0,8 F Backup time minimum 7 days at 25 °C Table 17: Data of RTC Page 22 of 41 Hardware Manual • Doc. No.: V.2030.21 / Rev. 1.2 XMC-CPU/T10... -
Page 23: Health
Table 19: Data of the memory interface 6.15 Software Support The flash memory carries the standard boot program “Das U-Boot” and enables the XMC-CPU/T10 to boot various operating systems from network or on-board SPI-Flash. BSPs are available from esd as described in the “Order Information” on page 40. -
Page 24: Firmware License
License information “3rd Party Licensor Notice” as part of the product documentation. esd provides the complete bootloader-source code on request. esd strives to restore all changes on the bootloader into the official sources. The homepage of the U-Boot project is: http://www.denx.de/wiki/U-Boot. -
Page 25: Connector Assignments
Pin Position: Pin Assignment: (X1220) (Input) Signal Description: +5 V power supply voltage D+, D-... USB signal lines Data+, Data- -... not connected GND... Reference potential XMC-CPU/T10 Hardware Manual • Doc. No.: V.2030.21 / Rev. 1.2 Page 25 of 41... -
Page 26: Ethernet Eth0, Eth1
MDIx+, MDIx- ... Ethernet data lines (x = 0 - 3) Shield... case shield, connected with the front panel of the XMC-CPU/T10. NOTICE Cables of category CAT5e or higher have to be used to grant the function in networks with 1000 Mbit/s. -
Page 27: Pmc Connectors
Connector Assignments 7.4 PMC Connectors The XMC-CPU/T10 uses the PMC connectors P1, P2 and P4. The assignment of the connectors P1 and P2 conforms with IEEE1386. P4 comes with a module-specific assignment. 7.4.1 PMC P1 Connector Signal Signal -12V INTA#... -
Page 28: Pmc P2 Connector
C/BE2# n.c. TRDY# +3.3V STOP# PERR# +3.3V SERR# C/BE1# AD[14] AD[13] M66EN AD[10] AD[08] +3.3V AD[07] n.c. +3.3V n.c. n.c. n.c. EREADY RESETOUT# n.c. +3.3V MONARCH# Page 28 of 41 Hardware Manual • Doc. No.: V.2030.21 / Rev. 1.2 XMC-CPU/T10... -
Page 29: Pmc P4 I/O Connector
3.3V or 2.5V, IO LVDS_B34_6_P FPGA-IO<28> 3.3V or 2.5V, IO LVDS_B34_16_N FPGA-IO<29> 3.3V or 2.5V, IO LVDS_B34_15_N FPGA-IO<30> 3.3V or 2.5V, IO LVDS_B34_16_P FPGA-IO<31> 3.3V or 2.5V, IO LVDS_B34_15_P XMC-CPU/T10 Hardware Manual • Doc. No.: V.2030.21 / Rev. 1.2 Page 29 of 41... - Page 30 0Ω resistors. INFORMATION For the usage of the LVDS signals, the coding switches have to be configured to 2.5V. See chapter “Coding Switches” on page 15. Page 30 of 41 Hardware Manual • Doc. No.: V.2030.21 / Rev. 1.2 XMC-CPU/T10...
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Page 31: Xmc - P5
17 GND 18 GND 18 n.c. 18 GND 18 GND 18 n.c. 18 REFCLK_0p 19 REFCLK_0n 19 n.c. 19 WAKE# 19 Root# 19 n.c. 19 XMC-CPU/T10 Hardware Manual • Doc. No.: V.2030.21 / Rev. 1.2 Page 31 of 41... -
Page 32: Xmc - P6
The name of the LVDS signals contains the bank, the pair and the polarity (P/N). Example: Signal name: LVDS B35-6-P → Bank: 35, Pair: 6, Polarity: P (+) Page 32 of 41 Hardware Manual • Doc. No.: V.2030.21 / Rev. 1.2 XMC-CPU/T10... -
Page 33: Jtag X900
Connector Assignments 7.7 JTAG X900 The JTAG interface has to be connected from the bottom side of the XMC-CPU/T10. esd offers two adapters, the XMC-CPU-ADAPTER-BDI and the XMC-CPU-ADAPTER-NXP as accessories. See Order Information on page 40 for more detail. 7.7.1 XMC-CPU-ADAPTER-BDI The XMC-CPU-ADAPTER-BDI (esd order No.: V.2029.02) is an interface to connect the Abatron... -
Page 34: Xmc-Cpu-Adapter-Nxp
Connector Assignments 7.7.2 XMC-CPU-ADAPTER-NXP The XMC-CPU-ADAPTER-NXP (esd order No.: V.2029.04) is an interface to connect the NXP (Health Controller) to the XMC-CPU/T10 connector X900. Samtec CLM <-> box header (16 pins) (6 pins) Figure 7: XMC-CPU/T10-ADAPTER-NXP NOTICE The 16-pole SMD strip has no inverse-polarity protection! Property damage may result due to incorrect adapter connection. -
Page 35: Debug Interface X400 And Jtag Fpga Interface X1900
Information on page 40. 7.8.1 XMC-CPU-ADAPTER-FPGA The XMC-CPU-ADAPTER-FPGA (esd order No.: V.2029.03) is an interface to connect the Tool XILINX ChipScope to the XMC-CPU/T10 connector X1900. Furthermore, the adapter can be used to connect X400 to a JTAG chain of the Health Controller and PCIe-to-PCI bridge. -
Page 36: Description Of The Units
Access via IFC (32-bit, local bus) 0xFF20 0000 0xFF30 0000 Access via IFC (16-bit, local bus) 0x9000 0000 0x9FFF FFFF Access via PCIe 1x Table 20: Access Addresses Page 36 of 41 Hardware Manual • Doc. No.: V.2030.21 / Rev. 1.2 XMC-CPU/T10... -
Page 37: Fpga
Xilinx: https://www.xilinx.com/ A Sample FPGA for the I/O configuration is included in delivery of the XMC-CPU/T10. With this Sample FPGA the following tables are valid: Offset addresses of the modules for the I/O access:... -
Page 38: Bootloader
The U-Boot source is available from esd on request. 9.2 Configuration and Console Access Use an USB cable with mini-B connector (XMC-CPU/T10 side) and type A connector (PC side) to connect the XMC-CPU/T10 to a PCs USB port. The U-Boot console is accessible via the front panel's USB 'CON' device port (mini-B socket). -
Page 39: Special Commands
9.3 Special Commands Command Description fpgaboot Programming the FPGA setled Setting LEDs testled Testing the LEDs health Functions for monitoring voltage/temperature Table 23: Special “Das U-Boot” commands XMC-CPU/T10 Hardware Manual • Doc. No.: V.2030.21 / Rev. 1.2 Page 39 of 41... -
Page 40: Order Information
XMC/PMC CPU with PowerPC QorIQ T1022, V.2030.01 1,2 GHz, FPGA, 2x GBit-Ethernet Accessories XMC-CPU-ADAPTER-BDI XMC-CPU-ADAPTER-BDI Interface to connect the Abatron BDI2000 and V.2029.02 BDI3000 to XMC-CPU/T10 XMC-CPU-ADAPTER-NXP XMC-CPU-ADAPTER-NXP Interface to NXP (Healthcontroller) V.2029.04 XMC-CPU/T10 XMC-CPU-ADAPTER-FPGA XMC-CPU-ADAPTER-FPGA Interface to connect the Tool XILINX V.2029.03... - Page 41 Object code, Runtime license for a single site For detailed information about the driver availability for your special operating system, please contact our sales team. Table 24: Order information PDF Manuals Please download the manuals as PDF documents from our esd website www.esd.eu for free. Manuals Order No.
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