1. Manuals
  2. Brands
  3. ESD Manuals
  4. Computer Hardware
  5. PMC-CPU/440
  6. User manual

ESD PMC-CPU/440 User Manual

Powerpc 440epx prpmc module
Hide thumbs
Table of Contents

Advertisement

Quick Links

Download this manual
PMC-CPU/440
Status: released
PMC-CPU/440
PowerPC 440EPx PrPMC module
__________
User Manual
Product Order No. V.2027.02-05
User Manual - V.2027.21
Revision 1.3
Page
All rights reserved.
Filename: PMC-
Copyright © esd gmbh 2012
2012-06-11
1 of 49
CPU440_Manual_en_13.odt

Advertisement

Table of Contents
loading
Need help?

Need help?

Do you have a question about the PMC-CPU/440 and is the answer not in the manual?

Questions and answers

Related Manuals for ESD PMC-CPU/440

Summary of Contents for ESD PMC-CPU/440

  • Page 1 PMC-CPU/440 Status: released PMC-CPU/440 PowerPC 440EPx PrPMC module __________ User Manual Product Order No. V.2027.02-05 User Manual - V.2027.21 Revision 1.3 Page All rights reserved. Filename: PMC- Copyright © esd gmbh 2012 2012-06-11 1 of 49 CPU440_Manual_en_13.odt...
  • Page 2 The information in this document has been carefully checked and is believed to be entirely reliable. esd makes no warranty of any kind with regard to the material in this document, and assumes no responsibility for any errors that may appear in this document. In particular descriptions and technical data specified in this document may not be constituted to be guaranteed product features in any legal sense.
  • Page 3 Responsible for content / author Name Company / Phone Email Department M. Fuchs esd gmbh / SD +49 511 37298 0 support@esd.eu Distribution / Review Name Firma / Abteilung Telefon Email User Manual - V.2027.21 All rights reserved. Revision 1.3...
  • Page 4 12, 13 48,49 2012-06-05 /AV renamed to "Declaration of Conformity" 10.1 Note to appendix removed Editorial revision 2012-06-11 /AV User Manual - V.2027.21 All rights reserved. Revision 1.3 Page Filename: PMC- Copyright © esd gmbh 2012 2012-06-11 4 of 49 CPU440_Manual_en_13.odt...
  • Page 5 ! The PMC-CPU/440 may become warm during normal use. Always allow adequate ventilation around the PMC-CPU/440 and use care when handling. ! Do not operate the PMC-CPU/440 adjacent to heat sources and do not expose it to unnecessary thermal radiation. Ensure an ambient temperature as specified in the technical data.

  • Page 6: Table Of Contents

    PMC-CPU/440 Status: released Contents 1 Overview............................8 1.1 Description Of The PMC-CPU/440 Module................8 1.2 Technical Data.......................... 9 1.2.1 General..........................9 1.2.2 CPU Core.......................... 9 1.2.3 Realtime Clock (RTC)......................9 1.2.4 PCI Interface........................10 1.2.5 Serial Interfaces....................... 10 1.2.6 CAN Interfaces......................... 10 1.2.7 Ethernet Interfaces......................
  • Page 7 11.6.1 Custom Module Conventions..................47 11.6.2 Sample Custom Module „simple_io“................47 12 EC Declaration of Conformity......................48 13 Ordering Information........................49 User Manual - V.2027.21 All rights reserved. Revision 1.3 Page Filename: PMC- Copyright © esd gmbh 2012 2012-06-11 7 of 49 CPU440_Manual_en_13.odt...

  • Page 8: Overview

    1 Overview 1.1 Description Of The PMC-CPU/440 Module The PMC-CPU/440 is a PMC module in ‘single’ PCI Mezzanine Card form factor. It can act as PMC monarch (PrPMC) or as non-monarch (adapter/target) board. Apart from a powerful CPU core the PowerPC 440EPx embedded processor integrates a DDR2 RAM controller, a PCI bus interface, a controller for serial interfaces and two gigabit Ethernet MACs.

  • Page 9: Technical Data

    148mm x 74mm weight ~ 140g (including heat sink) The PMC-CPU/440 is an industrial product and meets the demands of the EU regulations and EMC standards printed in the conformity declaration at the end of this manual. Warning: In a residential, commercial or light industrial...

  • Page 10: Pci Interface

    Bit rate 10 kbit/s ... 1 Mbit/s Bus termination None Connectors PMC P4 1 esd provides a suitable software driver for Linux or MS Windows PCs. User Manual - V.2027.21 All rights reserved. Revision 1.3 Page Filename: PMC- Copyright © esd gmbh 2012...

  • Page 11: Ethernet Interfaces

    Attention: Do not use longer screws because they might damage the PMC-CPU/440 ● mounting threads. The PMC-CPU/440 may only be used on PMC sites with 3.3V PCI signalling. Typically this is ● ensured by the correct IO-voltage coding holes in the PMC module and pins on the carrier system.

  • Page 12: Top And Bottom Side

    4 Top and Bottom Side The top side of the PMC-CPU/440 PCB is covered by a an aluminium heat sink on most areas. There are two 0,1“ contacts near the front panel. These can be used to install a strapping jumper. By default the jumper is not installed when the boards are shipped.
  • Page 13 4 Top and Bottom Side Status: released Fig. 3: Top view of the PMC module The PMC-CPU/440 has one additional LED on the bottom side of the PCB. This LEDs is visible when the PMC module is installed on a carrier board. LED designator...

  • Page 14: Jtag Debug Interface

    2 The JTAG connector is oriented with pin 1 close to the center of the PCB. The pin 1 drilling is marked by a tiny '1' on the PCB's solder side. User Manual - V.2027.21 Revision 1.3 Page All rights reserved. Filename: PMC- Copyright © esd gmbh 2012 2012-06-11 14 of 49 CPU440_Manual_en_13.odt...
  • Page 15 5 JTAG Debug Interface Status: released Fig. 5: self-build JTAG adapter inserted into PMC module from bottom side of PCB User Manual - V.2027.21 Revision 1.3 Page All rights reserved. Filename: PMC- Copyright © esd gmbh 2012 2012-06-11 15 of 49 CPU440_Manual_en_13.odt...

  • Page 16: Pmc Connectors

    6 PMC Connectors Status: released 6 PMC Connectors The PMC-CPU/440 module uses the PMC connectors P1, P2 and P4. P1 and P2 provide the PCI interface and power supply connection. P4 has a complete module specific pinout. 6.1 PMC P1 Connector...

  • Page 17: Pmc P2 Connector

    AD[10] AD[08] +3.3V AD[07] n.c. (REQB#) +3.3V GNTB# n.c. (reserved) n.c. (reserved) EREADY RESETOUT# n.c. (ACK64#) +3.3V MONARCH# User Manual - V.2027.21 Revision 1.3 Page All rights reserved. Filename: PMC- Copyright © esd gmbh 2012 2012-06-11 17 of 49 CPU440_Manual_en_13.odt...

  • Page 18: Pmc P4 I/O Connector

    6 PMC Connectors Status: released 6.3 PMC P4 I/O Connector P4 is used to interface many PMC-CPU/440 specific interfaces like the CAN buses, I2C and FPGA- I/Os. esd offers a PMC-PIM module with two isolated CAN physical circuits. 6.3.1 Pinout...

  • Page 19: Signal Description

    Do not connect to these signals! RS232: RS232 signals (logic-1: -9V, logic-0: +9V) ● RS485+/-: RS485 differential signals ● 6) The following 12 FPGA-I/O signals are only available on the PMC-CPU/440 ext. IO variant: FPGA-IO<32,34,36,38,40, 42-44, 45-47> ● 6.3.2 Signal Description Signal Name...

  • Page 20: Local Memory Map

    0x1.ef0f.ffff EBC bank 4 (PerCS4#): FPGA (32 bit bank, size=1MB) 0x1.ef00.0000 0x1.ef00.00ff FPGA internal registers (32bit bank) 0x1.ef01.n000 0x1.ef01.nfff esd's CAN IP cores (default: 2 IP cores; n=0..1) 0x1.ef08.0000 0x1.ef0f.ffff FPGA internal registers (reserved for custom extensions) 0x1.ef10.0000 0x1.ef1f.ffff EBC bank 5 (PerCS5#): FPGA (16 bit bank, size=1MB) 0x1.ef18.0000...
  • Page 21 - default FPGA bit file image (512KB) 0x1.fff8.0000 0x1.fff9.ffff - reserved (128KB) 0x1.fffa.0000 0x1.ffff.ffff - U-Boot bootloader (384KB) User Manual - V.2027.21 All rights reserved. Revision 1.3 Page Filename: PMC- Copyright © esd gmbh 2012 2012-06-11 21 of 49 CPU440_Manual_en_13.odt...

  • Page 22: Interrupts

    8.2.3 Asserting Local Interrupts From PCI Bus Method I: PCI master writes to PCI_COMMAND register. ● Method II:PCI master writes to the FPGA's HOSTCTRL register (see chap. 11.2) ● 9 PCI Configuration The PMC-CPU/440 uses the following PCI identification: Monarch (PrPMC) Non-Monarch Class/Subclasscode: Class/Subclasscode: 0x0600 (hostbridge)

  • Page 23: Bootloader

    GNU public license (GPL). Please see esd's „3 party licensor notice“ document that is part of the product's documentation for the full license text. You can contact esd for a copy of the full bootloader source code for the PMC-CPU/440.

  • Page 24: Default Bootloader Environment

    Variables can be modified through the setenv <name> [<value>] command and finally modifications can be stored in a non-volatile memory through saveenv. This is the factory default environment setup for the PMC-CPU/440 (only the most important variables are printed here): => printenv...

  • Page 25: Flash Update

    The bootloader update process is very delicate. Any mistake may result in a board that is not usable anymore and which must be shipped back to be reprogrammed by esd using a JTAG debugger. Here are step-by-step instructions for bootloader update at the serial console. The tftp command requires a correct U-Boot network configuration.

  • Page 26: Bsp Commands

    10.5 BSP Commands The following U-Boot BSP commands have been specially added to support the PMC-CPU/440 functions. Type help <command> at the bootloader prompt to get a short command reference. 10.5.1 irigb - Get / Set IRIG-B time The irigb command will display the current IRIG-B time (IRIG-B receiver + local IRIG-B generators time).

  • Page 27: Sbe - Configure Cpu Strapping

    CPU/440 will appear a short time after the device is powered on. This means that a terminal program on the PC cannot open the port before the PMC-CPU/440 module is powered on. With a suitable bringup delay the user has enough time to open the serial port from the terminal program without losing any startup messages.

  • Page 28: Loadpci - Start Pci Firmware Loading

    Command "0" bootm: The U-Boot loadaddr variable is set to the address parameter ● value. Then the bootm command is issued. User Manual - V.2027.21 All rights reserved. Revision 1.3 Page Filename: PMC- Copyright © esd gmbh 2012 2012-06-11 28 of 49 CPU440_Manual_en_13.odt...

  • Page 29: Fpga Command

    Typically you will need to add some more commands to the bootcmd variable (e.g. to start your operating system=. => setenv fpga fpga loadb 0 fff00000 => setenv bootcmd run fpga User Manual - V.2027.21 All rights reserved. Revision 1.3 Page Filename: PMC- Copyright © esd gmbh 2012 2012-06-11 29 of 49 CPU440_Manual_en_13.odt...

  • Page 30: Painit Command

    Attention: Never add this command to any bootloader variable that is automatically executed after power-on (e.g. preboot or bootcmd). This would lead to an uninterruptible reset loop. User Manual - V.2027.21 All rights reserved. Revision 1.3 Page Filename: PMC- Copyright © esd gmbh 2012 2012-06-11 30 of 49 CPU440_Manual_en_13.odt...

  • Page 31: Special Environment Variables

    The pram variable is used to reserve RAM that is not used by the bootloader. When pram is set, the variable mem is automatically set to the amount of available RAM (total RAM – pram). The reserved RAM is used by the esd PCIAccess driver. Pram must be set to the amount of reserved RAM in KiB.

  • Page 32: Fpga

    PMC-CPU/440 11 FPGA Status: released 11 FPGA The PMC-CPU/440 comes with a Xilinx Spartan 3E FPGA (part#: XC3S1200E-4FTG256C) installed. The FPGA provides several functions that are described in this chapter. 11.1 Functional Blocks IRIG-B • decoding of B100 time code format •...

  • Page 33: Fpga Registers

    IRIG_TIME register. This register is read- only. Bits Function (MSB) 31..17 unused 16..0 SBS (straight binary seconds) (0..86399) User Manual - V.2027.21 All rights reserved. Revision 1.3 Page Filename: PMC- Copyright © esd gmbh 2012 2012-06-11 33 of 49 CPU440_Manual_en_13.odt...
  • Page 34 0x0070 R/W DDFS control register / ADPLL phase error (see detailed description below) DDFSINC 0x0074 R/W DDFS increment value. User Manual - V.2027.21 All rights reserved. Revision 1.3 Page Filename: PMC- Copyright © esd gmbh 2012 2012-06-11 34 of 49 CPU440_Manual_en_13.odt...

  • Page 35: Register Description

    When set to '1' the RESET_EN and CLOCK_EN signals on CLKRST_EN_CSTM Pn4 (see above) are connected to the FPGA's custom module. Default after reset: '0' User Manual - V.2027.21 All rights reserved. Revision 1.3 Page Filename: PMC- Copyright © esd gmbh 2012 2012-06-11 35 of 49 CPU440_Manual_en_13.odt...
  • Page 36 (see timestamp unit) '011': RESET_OUT pulse is triggered by IRIG-B receiver unit (see chap. 11.3.4 For details). '100': esd internal test mode – do not use '111': RESET_OUT is connected to the FPGA's custom module. Default after reset: '000' The automatically timed reset pulse has about 6 us pulse width.
  • Page 37 Default after (FPGA-) reset: '00' reserved Default after (FPGA-) reset: '0' reserved Default after (FPGA-) reset: '0' User Manual - V.2027.21 All rights reserved. Revision 1.3 Page Filename: PMC- Copyright © esd gmbh 2012 2012-06-11 37 of 49 CPU440_Manual_en_13.odt...

  • Page 38: Status Register (0X0004)

    When set to '0' LEDB is pulsed by an interrupt coming from an odd (1,3,...) CAN IP core or by nIRQ2 from the FPGA's custom User Manual - V.2027.21 All rights reserved. Revision 1.3 Page Filename: PMC- Copyright © esd gmbh 2012 2012-06-11 38 of 49 CPU440_Manual_en_13.odt...

  • Page 39: Tsctrl - Timestamp Unit Control Register (0X0018)

    11.3.5 HOSTCTRL – Host control register (0x0060) Bits Name Function 31 .. 6 RESERVED Always read '0' PMCRSTOUT_GATE see PMCRSTOUT_FLAG User Manual - V.2027.21 All rights reserved. Revision 1.3 Page Filename: PMC- Copyright © esd gmbh 2012 2012-06-11 39 of 49 CPU440_Manual_en_13.odt...
  • Page 40 '1': unmask interrupts from the FIFO module. FIFO interrupts must also be enabled for each FIFO in the User Manual - V.2027.21 All rights reserved. Revision 1.3 Page Filename: PMC- Copyright © esd gmbh 2012 2012-06-11 40 of 49 CPU440_Manual_en_13.odt...

  • Page 41: Ddfs* - Clock Generator Registers (0X0070-0X0078)

    '1': reference clock is synchronized to IRIG-B input source. '0': reference clock is free running Default after (FPGA-) reset is: '0' User Manual - V.2027.21 All rights reserved. Revision 1.3 Page Filename: PMC- Copyright © esd gmbh 2012 2012-06-11 41 of 49 CPU440_Manual_en_13.odt...

  • Page 42: Fifo<0

    11.5 Using the FIFO module The PMC440 provides four hardware FIFOs that are implemented in the on-board FPGA. Each FIFO User Manual - V.2027.21 All rights reserved. Revision 1.3 Page Filename: PMC- Copyright © esd gmbh 2012 2012-06-11 42 of 49 CPU440_Manual_en_13.odt...
  • Page 43 /* check for interrupt from fifo module */ if (status & STATUS_FIFO_ISF) { /* disable/mask this int source */ FPGA_OUT32(&fpga->hostctrl, HOSTCTRL_FIFOIE_GATE); rc = 0; User Manual - V.2027.21 All rights reserved. Revision 1.3 Page Filename: PMC- Copyright © esd gmbh 2012 2012-06-11 43 of 49 CPU440_Manual_en_13.odt...
  • Page 44 } else if (!strcmp(argv[1],"wait")) { got_fifoirq = 0; irq_install_handler (FPGA_IRQ, (interrupt_handler_t *)fpga_interrupt, fpga); printf(" fifo level data\n"); printf("______________________________\n"); User Manual - V.2027.21 All rights reserved. Revision 1.3 Page Filename: PMC- Copyright © esd gmbh 2012 2012-06-11 44 of 49 CPU440_Manual_en_13.odt...
  • Page 45 /* get optional count parameter */ n = 1; if (argc >= 5) { n = (int)simple_strtoul(argv[4], NULL, 10); User Manual - V.2027.21 All rights reserved. Revision 1.3 Page Filename: PMC- Copyright © esd gmbh 2012 2012-06-11 45 of 49 CPU440_Manual_en_13.odt...

  • Page 46: Fpga Custom Module

    The FPGA custom module allows users to add customized functionality to the PMC440 onboard FPGA. For extending the PMC440 FPGA esd provides the following files (shipped in a zip archive) that have to be added to an Xilinx ISE design project: pmc440_cstm_fpga_r7/pmc440.vhd...

  • Page 47: Custom Module Conventions

    11.6.2 Sample Custom Module „simple_io“ The PMC-CPU/440 is shipped with a default FPGA image that includes the simple_io custom module. This module implements a simple GPIO controller for 48 usable FPGA I/Os that are available on the PMC's P4 connector.

  • Page 48: Ec Declaration Of Conformity

    PMC-CPU/440 12 EC Declaration of Conformity Status: released 12 EC Declaration of Conformity User Manual - V.2027.21 All rights reserved. Revision 1.3 Page Filename: PMC- Copyright © esd gmbh 2012 2012-06-11 48 of 49 CPU440_Manual_en_13.odt...

  • Page 49: Ordering Information

    Table 1: Order information PDF Manuals Manuals are available in English and usually in German as well. For availability of English manuals see table below. Please download the manuals as PDF documents from our esd website www.esd.eu for free. Manuals Order No.

Table of Contents