Aaeon GENE-TGU6 User Manual
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Aaeon GENE-TGU6 User Manual

3.5” subcompact board
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GENE-TGU6
3.5" Subcompact Board
st
User 's Manual 1
Ed
Last Updated: October 12, 2021

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Summary of Contents for Aaeon GENE-TGU6

  • Page 1 GENE-TGU6 3.5” Subcompact Board User ’s Manual 1 Last Updated: October 12, 2021...
  • Page 2 AAEON assumes no liabilities resulting from errors or omissions in this document, or from the use of the information contained herein. AAEON reserves the right to make changes in the product design without notice to its users.
  • Page 3 Acknowledgements All other products’ name or trademarks are properties of their respective owners. Microsoft Windows is a registered trademark of Microsoft Corp. ⚫ Intel® and Celeron® are registered trademarks of Intel Corporation ⚫ Intel Core™ are trademarks of Intel Corporation ⚫...
  • Page 4 Packing List Before setting up your product, please make sure the following items have been shipped: I t em Quantity GENE-TGU6 MB If any of these items are missing or damaged, please contact your distributor or sales representative immediately. Preface...
  • Page 5 (if any), its specifications, dimensions, jumper/connector settings/definitions, and driver installation instructions (if any), to facilitate users in setting up their product. Users may refer to the product page at AAEON.com for the latest version of this document. Preface...
  • Page 6 Saf e ty Precautions Please read the following safety instructions carefully. It is advised that you keep this manual for future references All cautions and warnings on the device should be noted. Make sure the power source matches the power rating of the device. Position the power cord so that people cannot step on it.
  • Page 7 If any of the following situations arises, please the contact our service personnel: Damaged power cord or plug Liquid intrusion to the device iii. Exposure to moisture Device is not working as expected or in a manner as described in this manual The device is dropped or damaged Any obvious signs of damage displayed on the device...
  • Page 8 FCC Statement This device complies with Part 15 FCC Rules. Operation is subject to the following two conditions: (1) this device may not cause harmful interference, and (2) this device must accept any interference received including interference that may cause undesired operation.
  • Page 9 Chi na RoHS Requirements ( CN) 产品中有毒有害物质或元素名称及含量 AAEON Main Board/ Daughter Board/ Backplane 有毒有害物质或元素 部件名称 铅 汞 镉 六价铬 多溴联苯 多溴二苯醚 (Pb) (Hg) (C d) (C r(VI)) (PBB) (PBDE) 印刷电路板 ○ ○ ○ ○ ○ ○ 及其电子组件 外部信号 ○ ○...
  • Page 10 Chi na RoHS Requirement (EN) Poisonous or Hazardous Substances or Elements in Products AAEON Main Board/ Daughter Board/ Backplane Poisonous or Hazardous Substances or Elements He xavalent Polybrominated Polybrominated C omponent Le ad Me rcury C admium C hromium Biphenyls...

  • Page 11: Table Of Contents

    Table of Contents Chapter 1 - Product Specifications..............1 Specifications ....................
  • Page 12 2.4.27 USB3.2 Gen 2 Ports 3 & 4 Dual Connector (CN35) ......41 2.4.28 i219 LED Connector (CN36)..............42 2.4.29 i225 LED Connector (CN37) ..............42 Thermal Solutions ..................43 2.5.1 GENE-TGU6-FAN01 ................43 2.5.2 GENE-TGU6-HSK01 ................45 2.5.3 GENE-TGU6-HSP01 ................47 Chapter 3 - AMI BIOS Setup.
  • Page 13 3.4.5 PCH-FW Configuration................ 64 3.4.5.1 Firmware Update Configuration ..........65 3.4.6 Power Management ................66 3.4.7 AAEON BIOS Robot................67 3.4.7.1 Device Detecting Configuration..........69 3.4.8 TSN GBE Configuration ............... 83 Setup Submenu: System I/O................ 84 3.5.1 PCI Express Configuration ..............85 3.5.2...
  • Page 14 3.6.1.1 Key Management ..............103 Setup Submenu: Boot .................105 3.7.1 BBS Priorities ..................106 Setup Submenu: Save & Exit...............107 Chapter 4 – Driver Installation..............108 Driver Download/Installation ..............109 Appendix A - I/O Information .

  • Page 15: Chapter 1 - Product Specifications

    Chapter 1 Chapter 1 - Product Specifications...

  • Page 16: Specifications

    1 .1 Spe cifications System F o rm Factor 3.5" Subcompact Board CP U Intel® 11th Generation Core™/ Celeron CPU: Core i7-1185G7E (4C/8T, 1.80GHz, up to 4.40GHz) Core i5-1145G7E (4C/8T, 1.50GHz, up to 4.10GHz) Core i3-1115G4E (2C/4T, 2.20GHz, up to 3.90GHz) Celeron®...
  • Page 17 Powe r P o wer Requirement +9 ~ 36V (Optional: +12V) P o wer Supply Type AT/ATX Co nnector Phoenix 2-pin Connector P o wer Consumption (Typical) 4.96A at +12V, Intel® i7-1185G7E, DDR4 3200MHz 32GB x 2 P o wer Consumption (Max) 7.32A at +12V, Intel®...
  • Page 18 E xternal I/O Et hernet Intel® i219LM, 10/100/1000Base, RJ-45 x 1 Intel® i225LM, 100/1000/2500Base, RJ-45 x 1 U SB USB3.2 Gen 2 x 4 USB3.2 Gen 2 Type C x 1 (PD 5V/3A) Serial Port — Vid eo HDMI 2.0b x 1 DP1.4a x 2 Type C DP1.4 x 1 P o wer Input...
  • Page 19 E xpansion Mini PCIe/ mSATA Full-Sized mSATA/mPCIe x 1 (default: mSATA, select with BIOS) M. 2 M-Key 2280 x 1 (PCIe [x4]) E-Key 2230 x 1 (PCIe, USB2.0) B I O — Ot her — Me chanical Dimensions 5.75” x 4” (146mm x 101.7mm) E nvironmental Op erating Temperature 32°F ~ 140°F (0°C ~ 60°C)

  • Page 20: Block Diagram

    1 .2 Bl ock Diagram Chapter 1 – Product Specifi c ations...

  • Page 21: Chapter 2 - Hardware Information

    Chapter 2 Chapter 2 – Hardware Information...

  • Page 22: Dimensions

    Di mensions Chapter 2 – Hardware Information...

  • Page 23: Jumpers And Connectors

    2.2 Jum pers and Connectors To p View F ront I/O View Chapter 2 – Hardware Information...
  • Page 24 B o ttom View Thermal Source 2 Front I/O Chapter 2 – Hardware Information...

  • Page 25: List Of Jumpers

    2.3 Li st of Jumpers Please refer to the table below for all of the board’s jumpers that you can configure for your application Lab el F unction JP 1 Front Panel Connector JP 2 Touch Screen 4/5/8-wire Mode Selection Auto Power Button Enable/ Disable Selection JP 3 JP 4...

  • Page 26: Touch Screen 4, 5, 8-Wire Selection (Jp2)

    2.3.2 Touch Screen 4, 5, 8-Wire Selection (JP2) 4/8-Wire Mode 5-Wire Mode (Default) 2.3 .3 Auto Power Button E nable/Disable Selection (JP 3) Disable/ Enable/ ATX Power Mode AT Power Mode (Default) 2.3.4 COM2 Pin8 Function Selection ( JP4) +12V Ring (Default) 2.3.5 LVDS/eDP Backlight Inverter VCC &...

  • Page 27: Lvds/Edp Port Backlight Lightness Co Ntrol Mode Selection (Jp6)

    2.3.6 LVDS/eDP Port Backlight Lightness Control Mode Selection ( JP6) VR Mode PWM Mode (Default) 2.3.7 Cl e ar CMOS Jumper ( JP7) Normal (Default) Clear CMOS Chapter 2 – Hardware Information...

  • Page 28: List Of Connectors

    2.4 Li st of Connectors Please refer to the table below for all of the board’s connectors that you can configure for your application Lab el F unction CN 1 +5V Output for SATA HDD CN 2 SATA Port CN 3 External Power Input CN 5 Audio I/O Port...

  • Page 29: Output For Sata Hdd (Cn1)

    Lab el F unction CN 30 Type C Connector (USB3.2 Gen 2 Only) CN 31 Battery Connector CN 32 SPI BIOS Debug Port CN 33 M.2 M Key 2280 CN 35 USB3.2 Gen 2 Port 3, Port 4, Dual Port Connector CN 36 i219 LED Connector CN 37...

  • Page 30: Sata Port (Cn2)

    2.4.2 SATA Port (CN2) P in P in Name Sig nal Type Sig nal Level SATA_TX+ DIFF SATA_TX- DIFF SATA_RX- DIFF SATA_RX+ DIFF 2.4.3 E xternal Power Input ( CN3) P in P in Name Sig nal Type Sig nal Level +12V +9~+36V (or +12V) at 8A N o te: There are two types of power input, 9~36V or 12V (by BOM option).

  • Page 31: Audio I/O Port (Cn5)

    2.4.4 Audi o I/O Port (CN5) P in P in Name Sig nal Type LOUT_R MIC_R LOUT_L MIC_L JD_LOUT JD_MIC AUD_GND AUD_GND JD_LIN LIN_R +VDD_AUD LIN_L Chapter 2 – Hardware Information...

  • Page 32: External +5Vsb Input (Cn6)

    2.4.5 E xternal +5VSB Input ( CN6) P in P in Name Sig nal Type Sig nal Level PS_ON# +5VSB +5V at 2A 2.4.6 DDR SO-DIMM Slot (CN7) Standard Specifications Chapter 2 – Hardware Information...

  • Page 33: Com Port 3, Port 4 Dual Header (Cn8)

    2.4.7 COM Port 3, Port 4 Dual Header (CN8) R S-232 P in P in P in Name Sig nal Type Sig nal Level ±5V ±5V ±5V Chapter 2 – Hardware Information...
  • Page 34 RS-485 P in P in P in Name Sig nal Type Sig nal Level RS485_D- ±5V RS485_D+ ±5V RS-422 P in P in P in Name Sig nal Type Sig nal Level RS422_TX- RS422_TX+ ±5V RS422_RX+ RS422_RX- Chapter 2 – Hardware Information...

  • Page 35: Mini Card Slot (Full-Size) (Cn10)

    2.4.8 Mi ni Card Slot ( Full-Size) ( CN10) P in P in Name Sig nal Type Sig nal Level PCIE_WAKE# +3.3VSB +3.3V +1.5V +1.5V PCIE_CLK_REQ# UIM_PWR UIM_DATA PCIE_REF_CLK- DIFF UIM_CLK PCIE_REF_CLK+ DIFF UIM_RST UIM_VPP W_DISABLE# +3.3V PCIE_RST# +3.3V PCIE_RX- DIFF +3.3VSB +3.3V...
  • Page 36 P in P in Name Sig nal Type Sig nal Level PCIE_RX+ DIFF +1.5V +1.5V SMB_CLK +3.3V PCIE_TX- DIFF SMB_DATA +3.3V PCIE_TX+ DIFF USB_D- DIFF USB_D+ DIFF +3.3VSB +3.3V +3.3VSB +3.3V +1.5V +1.5V Chapter 2 – Hardware Information...

  • Page 37: Ddr So-Dimm Slot (Cn11)

    P in P in Name Sig nal Type Sig nal Level +3.3VSB +3.3V 2.4.9 DDR SO-DIMM Slot (CN11) Standard Specifications 2.4.10 M.2 E-Key 2230 ( CN12) Standard Specifications 2.4.11 COM Port 1, Port 2 Dual Header ( CN13) R S-232 P in P in P in Name...
  • Page 38 P in P in P in Name Sig nal Type Sig nal Level ±5V RI/+5V/+12V N o te: RI/+5V/+12V for COM2 only. RS-485 P in P in P in Name Sig nal Type Sig nal Level RS485_D- ±5V RS485_D+ ±5V RS-422 P in P in...

  • Page 39: Touchscreen Connector (Optional) (Cn15)

    P in P in P in Name Sig nal Type Sig nal Level N o te 1: COM2 RS-232/422/485 can be set by BIOS setting. Default is RS-232. N o te 2: Pin 8 function can be set by JP4 (See Ch 2.3.4). 2.4.12 Touchscreen Connector (Optional) ( CN15) N o te: Touch mode can be set by BIOS.
  • Page 40 4- W ire Mode P in P in Name Sig nal Type Sig nal Level BOTTOM LEFT RIGHT Chapter 2 – Hardware Information...
  • Page 41 5- W ire Mode P in P in Name Sig nal Type Sig nal Level UL(Y) UR(H) LL(L) LR(X) SENSE(S) N o te: Touch Mode can be set by BIOS Chapter 2 – Hardware Information...

  • Page 42: Espi Debug Port (Cn16)

    2.4.13 e SPI Debug Port (CN16) P in P in Name Sig nal Type Sig nal Level LAD0 +3.3V LAD1 +3.3V LAD2 +3.3V LAD3 +3.3V +3.3V +3.3V LFRAME# LRESET# +3.3V LCLK SMB_DATA/I2C_SDA SMB_CLK/I2C_CLK SMB_ALERT/SERIRQ +3.3V Chapter 2 – Hardware Information...

  • Page 43: Digital I/O Connector (Cn17)

    2.4.14 Di gital I/O Connector ( CN17) P in Sig nal Description P in Sig nal Description +V5S (0.5A) 2.4.15 LVDS/eDP Port ( CN18) N o te: LVDS LCD_PWR can be set to +3.3V or +5V by JP5. (See Ch 2.3.5) N o te: LVDS LCD_PWR supports current of 2A Chapter 2 –...
  • Page 44 P in LVDS Sig nal Type Sig nal Level BKL_ENABLE BKL_ENABLE BKL_CONTROL BKL_CONTROL LCD_PWR LCD_PWR +3.3V/+5V LVDS_A_CLK- eDP_TXN3 DIFF LVDS_A_CLK+ eDP_TXP3 DIFF LCD_PWR LCD_PWR +3.3V/+5V LVDS_DA0- eDP_TXN2 DIFF LVDS_DA0+ eDP_TXP2 DIFF LVDS_DA1- eDP_TXN1 DIFF LVDS_DA1+ eDP_TXP1 DIFF LVDS_DA2- eDP_TXN0 DIFF LVDS_DA2+ eDP_TXP0 DIFF...

  • Page 45: Nano Sim Card Socket (Cn19)

    P in LVDS Sig nal Type Sig nal Level LCD_PWR LCD_PWR +3.3V/+5V LVDS_B_CLK- DIFF LVDS_B_CLK+ DIFF 2.4.16 Nano SIM Card Socket (CN19) P in P in Name Sig nal Type Sig nal Level UIM_PWR UIM_RST UIM_CLK UIM_VPP UIM_DATA Chapter 2 – Hardware Information...

  • Page 46: Usb 2.0 Port 5, Port 6 Dual Header (Cn21)

    2.4.17 USB 2.0 Port 5, Port 6 Dual Header (CN21) U SB Port 5 U SB Port 6 P in P in Name P in P in Name +5VSB (0.5A) +5VSB (0.5A) USB5_D- USB6_D- USB5_D+ USB6_D+ Chapter 2 – Hardware Information...

  • Page 47: Lvds/Edp Port Inverter/ Backlight Connector (Cn22)

    2.4.18 LVDS/eDP Port Inverter/ Backlight Connector (CN22) P in P in Name Sig nal Type Sig nal level BKL_PWR +5V / +12V BKL_PWR +5V / +12V BKL_CONTROL BKL_ENABLE +3.3V N o te 1: LVDS BKL_PWR can be set to +5V or +12V by JP5. (See Ch 2.3.5) N o te 2: LVDS BKL_PWR supports current of 1.5A N o te 3: LVDS BKL_CONTROL can be set by JP6.

  • Page 48: Cpu Fan (Cn23)

    2.4.19 CPU Fan (CN23) P in P in Name Sig nal Type Sig nal Level FAN_POWER +12V at 1A FAN_TAC FAN_CTL 2.4.20 USB 3.2 Gen 2 Ports 1 & 2 Dual Connector ( CN26) P in P in Name Sig nal Type Sig nal Level +5VSB +5V at 0.9A...

  • Page 49: Lan (Rj-45) Dual Port I225 And I219 (Cn27)

    P in P in Name Sig nal Type Sig nal Level USB0_SSTX− DIFF USB0_SSTX+ DIFF +5VSB +5V at 0.9A USB1_D- DIFF USB1_D+ DIFF USB1_SSRX− DIFF USB1_SSRX+ DIFF USB1_SSTX− DIFF USB1_SSTX+ DIFF 2.4.21 L AN ( RJ-45) Dual Port i225 and i 219 ( CN27) i225 i219 P in...

  • Page 50: Dp Connector (Cn28)

    i225 i219 P in P in Name P in P in Name 1P 8 LAN2_MDI2_N 2P 8 LAN1_MDI2_N 1P 9 LAN2_MDI3_P 2P 9 LAN1_MDI3_P 1P 10 LAN2_MDI3_N 2P 10 LAN1_MDI3_N 2.4.22 DP Connector (CN28) P in P in Name Sig nal Type Sig nal Level DP1_TX0_DP DIFF...

  • Page 51: Dp + Hdmi Connector (Cn29)

    P in P in Name Sig nal Type Sig nal Level DP1_AUX_DP DP1_AUX_DN DP1_HPD +V3P3S +3.3V 2.4.23 DP + HDMI Connector (CN29) P in P in Name Sig nal Type Sig nal Level DP Port DP2_TX0_DP DIFF DP2_TX0_DN DIFF DP2_TX1_DP DIFF DP2_TX1_DN DIFF...
  • Page 52 P in P in Name Sig nal Type Sig nal Level DP2_TX2_DN DIFF DP2_TX3_DP DIFF DP2_TX3_DN DIFF DP2_AUX_DP DP2_AUX_DN DP2_HPD +V3P3S +3.3V HDMI Port HDMI_TX2+ DIFF HDMI_TX2- DIFF HDMI_TX1+ DIFF HDMI_TX1- DIFF HDMI_TX0+ DIFF HDMI_TX0- DIFF HDMI_CLK+ DIFF HDMI_CLK- DIFF Chapter 2 –...

  • Page 53: Battery Connector (Cn31)

    P in P in Name Sig nal Type Sig nal Level DDC_CLK DDC_DATA HDMI_HPD 2.4.24 Battery Connector ( CN31) P in P in Name Sig nal Type Sig nal Level +3.3V 3.3V Chapter 2 – Hardware Information...

  • Page 54: Spi Bios Debug Port (Cn32)

    2.4.25 SPI BIOS Debug Port (CN32) P IN 1 P IN 2 P IN 3 P IN 4 P IN 5 P IN 6 P IN 7 P in P in Name Sig nal Type Sig nal Level SPI_MISO SPI_CLK +3.3VSB +3.3V SPI_MOSI...

  • Page 55: Usb3.2 Gen 2 Ports 3 & 4 Dual Connector (Cn35)

    2.4.27 USB3.2 G en 2 Ports 3 & 4 Dual Connector (CN35) P in P in Name Sig nal Type Sig nal Level +5VSB +5V at 0.9A USB2_D- DIFF USB2_D+ DIFF USB2_SSRX− DIFF USB2_SSRX+ DIFF USB2_SSTX− DIFF USB2_SSTX+ DIFF +5VSB +5V at 0.9A USB3_D- DIFF...

  • Page 56: I219 Led Connector (Cn36)

    2.4.28 i 219 LED Connector (CN36) P in P in Name Sig nal Type Sig nal Level LINK_ACT# +V3P3A +3.3V LAN_1000# LAN_100# LAN_100# LAN_1000# 2.4.29 i 225 LED Connector ( CN37) P in P in Name Sig nal Type Sig nal Level LINK_ACT# +V3P3A +3.3V...

  • Page 57: Thermal Solutions

    2.5 T he rmal Solutions 2.5.1 G E NE-TGU6-FAN01 Single piece cooler, does not require use of heat spreader Chapter 2 – Hardware Information...
  • Page 58 G E NE-TGU6-FAN01 Assembly Chapter 2 – Hardware Information...

  • Page 59: Gene-Tgu6-Hsk01

    2.5.2 G E NE-TGU6-HSK01 Single-piece heat sink, does not require use of heat spreader. Chapter 2 – Hardware Information...
  • Page 60 GEN E-TGU6-HSK01 Assembly Chapter 2 – Hardware Information...

  • Page 61: Gene-Tgu6-Hsp01

    2.5.3 G E NE-TGU6-HSP01 Chapter 2 – Hardware Information...
  • Page 62 GEN E-TGU6-HSP01 Assembly Chapter 2 – Hardware Information...

  • Page 63: Chapter 3 - Ami Bios Setup

    Chapter 3 Chapter 3 - AMI BIOS Setup...

  • Page 64: System Test And Initialization

    System Test and Initialization The GENE-TGU6 board uses certain routines to perform testing and initialization during the boot up sequence. If an error, fatal or non-fatal, is encountered, the module will output a few short beeps or display an error message. The module can usually continue the boot up sequence with non-fatal errors.

  • Page 65: Ami Bios Setup

    3.2 AMI BIOS Setup The AMI BIOS ROM has a pre-installed Setup program that allows users to modify basic system configurations, which is stored in the battery-backed CMOS RAM and BIOS NVRAM so that the information is retained when the power is turned off. To enter BIOS Setup, press <Del>...

  • Page 66: Setup Submenu: Main

    3.3 Se tup Submenu: Main Chapter 3 – AMI BIOS Setup...

  • Page 67: Setup Submenu: Advanced

    3.4 Se tup Submenu: Advanced Op tions Summary I n-Band ECC Support Disabled Enabled Optimal Default; Failsafe Default Enable/Disabled In-Band ECC Support I n-Band ECC Error Enabled I njection Disabled Optimal Default, Failsafe Default By enabling this Error Injection feature, the user acknowledges the security risks. Enabling Error Injection allows attackers who have access to the Host Operating System to inject IBECC errors that can cause unintended memory corruption and enable the leak of security data in the BIOS stolen memory regions.
  • Page 68 Op tions Summary I B ECC Protect Region 0-7 Disabled Optimal Default, Failsafe Default Enabled Enable/Disabled In-Band ECC for Region 0-7 N o te: In-Band ECC Support availability depends on CPU. Chapter 3 – AMI BIOS Setup...

  • Page 69: Graphics Configuration

    3.4.1 G raphics Configuration Chapter 3 – AMI BIOS Setup...

  • Page 70: Lvds Panel Configuration

    3.4.1.1 LVDS Panel Configuration Op tions Summary LVDS/eDP Disabled Optimal Default, Failsafe Default Enabled Enable/Disabled this panel. LVDS Panel Type 640X480@60HZ 800X480@60HZ 800X600@60HZ 1024X600@60HZ 1024X768@60HZ Optimal Default, Failsafe Default 1280X768@60HZ 1280X800@60HZ 1280X1024@60HZ 1366X768@60HZ 1440X900@60HZ 1600X1200@60HZ 1920X1080@60HZ 1920X1200@60HZ Chapter 3 – AMI BIOS Setup...
  • Page 71 Op tions Summary Select LCD panel used by Internal Graphics Device by selecting the appropriate setup item. Co lor Depth 18-bit Optimal Default, Failsafe Default 24-bit 36-bit 48-bit Select panel type B acklight Mode BIOS & Application Windows Slider Optimal Default, Failsafe Default Select backlight control signal type B acklight Type Normal...
  • Page 72 Op tions Summary Swing Level 450mV Select Swing Level Cent er Spreading Depth no spreading Optimal Default, Failsafe Default 0.5% 1.0% 1.5% 2.0% 2.5% Select Center Spreading Depth Chapter 3 – AMI BIOS Setup...

  • Page 73: Cpu Configuration

    3.4.2 CPU Configuration Op tions Summary I nt el (VMX) Virtualization Disabled Technology Enabled Optimal Default, Failsafe Default When enabled, a VMM can utilize the additional hardware capabilities provided by Vanderpool Technology. I nt el(R) SpeedStep(tm) Disabled Enabled Optimal Default, Failsafe Default Allows more than two frequency ranges to be supported.

  • Page 74: Memory Config Uration

    3.4.3 Me mor y Configuration Chapter 3 – AMI BIOS Setup...

  • Page 75: Hardware Monitor

    3.4.4 Hardware Monitor Op tions Summary Smart Fan Disabled Enabled Optimal Default, Failsafe Default Enable or Disable Smart Fan Chapter 3 – AMI BIOS Setup...

  • Page 76: Smart Fan Mode Configuration

    3.4.4.1 Sm ar t Fan Mode Configuration A uto Duty Cycle Mode Op tions Summary FAN1 Output Mode Output PWM mode (push pull) Linear Fan Application Output PWM mode Optimal Default, Failsafe Default (open drain) Output PWM mode (push pull) to control 4-wire fans.\nLinear fan application circuit to control 3-wire fan speed by fan’s power terminal.\nOutput PWM mode (open drain) to control Intel 4-wire fans.
  • Page 77 Op tions Summary Dut y Cycle Auto fan speed control. Fan speed will follow different temperature by different duty cycle 1-100 Temperature Manual Duty Mode Op tions Summary Manual Duty Mode Optimal Default, Failsafe Default Manual mode fan control, user can write expected duty cycle (PWM fan type) 1-100 Chapter 3 –...

  • Page 78: Pch-Fw Configuration

    3.4.5 PCH-FW Configuration Chapter 3 – AMI BIOS Setup...

  • Page 79: Firmware Update Configuration

    3.4.5.1 Fi rmware Update Configuration Op tions Summary Me F W Image Re-Flash Disabled Optimal Default, Failsafe Default Enabled Enable/Disable Me FW Image Re-Flash function. F W Update Disabled Enabled Optimal Default, Failsafe Default Enable/Disable ME FW Update function. Chapter 3 – AMI BIOS Setup...

  • Page 80: Power Management

    3.4.6 Powe r Management Op tions Summary Po wer Mode ATX Type Optimal Default, Failsafe Default AT Type Select system power mode R estore AC Power Loss Last State Optimal Default, Failsafe Default Always On Always Off IO Restore AC power Loss R TC wake system from S5 Disable Optimal Default, Failsafe Default...

  • Page 81: Aaeon Bios Robot

    3.4.7 AAE ON BIOS Robot Op tions Summary Sends watch dog before Disabled Optimal Default, Failsafe Default B I OS POST Enabled Enabled - Robot set Watch Dog Time r(WDT) right after power on, before BIOS start POST process. Robot will clear WDT on completion of POST. WDT will reset system automatically if it is not cleared before its timer counts down to zero.
  • Page 82 Op tions Summary OS Timer (minute) Optimal Default, Failsafe Default Timer count set to Watch Dog Timer for OS loading. Delayed POST (PEI phase) Disabled Optimal Default, Failsafe Default Enabled Enabled - Robot holds BIOS from starting POST, right after power on. This allows BIOS POST to start with stable power or start after system is physically warmed -up.

  • Page 83: Device Detecting Configuration

    3.4.7.1 De vice Detecting Configuration Action: Rest System Op tions Summary A ction Reset System Optimal Default, Failsafe Default Hold System Select action that robot should do. So ft or hard reset Soft Optimal Default, Failsafe Default Hard Select reset type robot should send on each boot. R etry-Count Optimal Default, Failsafe Default Fill retry counter here.
  • Page 84 Action: Hold System Op tions Summary A ction Reset System Optimal Default, Failsafe Default Hold System Select action that robot should do. Ho lding time out Optimal Default, Failsafe Default (s econd) Fill hold time out here. Robot will hold system no longer then time-out value, and then let system continue its POST.
  • Page 85 3.4.7.1.1 De vice # Detecting Configuration Interface: Disabled Op tions Summary I nt erface Disabled Optimal Default, Failsafe Default SMBUS Legacy I/O Super I/O MMIO Select interface robot should use to communicate with device. Chapter 3 – AMI BIOS Setup...
  • Page 86 Interface: PCI Op tions Summary B U S Optimal Default, Failsafe Default Fill BUS number to a PCI device, in hexadecimal. Range: 0 - FF Device Optimal Default, Failsafe Default Fill DEVICE number to a PCI device, in hexadecimal. Range: 0 - FF F unction Optimal Default, Failsafe Default Fill FUNCTION number to a PCI device, in hexadecimal.
  • Page 87 Op tions Summary R egister data is bitwise equal to Optimal Default, Failsafe Default bytewise equal to bytewise lesser than bytewise larger than Select how robot should compare data read from register, to a value configured below. R egister offset Optimal Default, Failsafe Default Fill register offset (or index) for robot to read, in hexadecimal.
  • Page 88 Interface: DIO Op tions Summary Device Is not Optimal Default, Failsafe Default Select that robot should or should not do action if condition met. DI O pin number DIO1 Optimal Default, Failsafe Default DIO* Fill DIO pin number. 0 - DIO0, 1 - DIO1, and so on. For COM express product: 0-3 - GPI0-3, 4-7 - GPO0-3 Device Is not...
  • Page 89 Interface: SMBUS Op tions Summary SMBUS Slave Address Optimal Default, Failsafe Default Fill slave address to a SMBUS device, in hexadecimal. Range: 0 - FF Device Is not Optimal Default, Failsafe Default Select that robot should or should not do action if condition met. I n co ndition Present Optimal Default, Failsafe Default...
  • Page 90 Op tions Summary R egister offset Optimal Default, Failsafe Default Fill register offset (or index) for robot to read, in hexadecimal. Range: 0 - FF B it offset Optimal Default, Failsafe Default Fill bit offset for register, for robot to compare with bit value. B it value Optimal Default, Failsafe Default High...
  • Page 91 Interface: Legacy I/O Op tions Summary I /O Address Optimal Default, Failsafe Default Fill I/O address device is responding to. Range: 0~FFFF Device Is not Optimal Default, Failsafe Default Select that robot should or should not do action if condition met. I n co ndition Present Optimal Default, Failsafe Default...
  • Page 92 Op tions Summary B it offset Optimal Default, Failsafe Default Fill bit offset for register, for robot to compare with bit value. B it value Optimal Default, Failsafe Default High Fill bit value for robot to compare register-bit with specified offset. B yt e value Optimal Default, Failsafe Default Fill a byte value for robot to compare register data with, in hexadecimal.
  • Page 93 Interface: Super I/O Op tions Summary Sup er I/O LDN Optimal Default, Failsafe Default Fill LDN number to a Super I/O device. Range: 0~FF Device Is not Optimal Default, Failsafe Default Select that robot should or should not do action if condition met. I n co ndition Present Optimal Default, Failsafe Default...
  • Page 94 Op tions Summary R egister offset Optimal Default, Failsafe Default Fill register offset (or index) for robot to read, in hexadecimal. Range: 0 - FF B it offset Optimal Default, Failsafe Default Fill bit offset for register, for robot to compare with bit value. B it value Optimal Default, Failsafe Default High...
  • Page 95 Interface: MMIO Op tions Summary MMI O Address Optimal Default, Failsafe Default Fill Memory Mapped I/O address device is responding to. Range: 0~FFFFFFFF Device Is not Optimal Default, Failsafe Default Select that robot should or should not do action if condition met. I n co ndition Present Optimal Default, Failsafe Default...
  • Page 96 Op tions Summary B it offset Optimal Default, Failsafe Default Fill bit offset for register, for robot to compare with bit value. B it value Optimal Default, Failsafe Default High Fill bit value for robot to compare register-bit with specified offset. B yt e value Optimal Default, Failsafe Default Fill a byte value for robot to compare register data with, in hexadecimal.

  • Page 97: Tsn Gbe Configuration

    3.4.8 T SN G BE Configuration Op tions Summary P CH TSN LAN Enabled Optimal Default, Failsafe Default Co ntroller Disabled Enable/Disable TSN LAN Enable Timed TSN Disabled Optimal Default, Failsafe Default P CS Enabled Enable/Disable TSN PCS. When enabled, TSN PCS device will appear in ACPI table P CH TSN Multi-Vc Disabled Optimal Default, Failsafe Default...

  • Page 98: Setup Submenu: System I/O

    3.5 Se tup Submenu: System I/O Chapter 3 – AMI BIOS Setup...

  • Page 99: Pci Express Configuration

    3.5.1 PCI E xpress Configuration Op tions Summary P CI Express Root Port 5 Enabled Optimal Default, Failsafe Default (CN 12) / Port11 Disabled Control the PCI Express Root Port. P CI e Speed Auto Optimal Default, Failsafe Default Gen1 Gen2 Gen3 Control the PCI Express Speed...

  • Page 100: Storage Configuration

    3.5.2 Storage Configuration Op tions Summary SATA Controller(s) Disabled Enabled Optimal Default, Failsafe Default Enable/Disable SATA Device. Po rt 0 / 1 Disabled Enabled Optimal Default, Failsafe Default Enable or Disable SATA Port Ho t Plug Disabled Optimal Default, Failsafe Default Enabled Designates this port as Hot Pluggable.

  • Page 101: Nvme Configuration

    3.5.2.1 NVMe Configuration Chapter 3 – AMI BIOS Setup...

  • Page 102: Hd Audio Subsystem Configuration Settings

    3.5.3 HD Audio Subsystem Configuration Settings Op tions Summary HD A udio Disabled Enabled Optimal Default, Failsafe Default Control Detection of the HD-Audio device. Disabled = HDA will be unconditionally disabled Enabled = HDA will be unconditionally enabled. Chapter 3 – AMI BIOS Setup...

  • Page 103: Digital Io Port Config Uration

    3.5.4 Di gital IO Port Configuration Op tions Summary DI O Port # Output Input Set DIO as Input or Output Out put Level High Optimal Default, Failsafe Default Set output level when DIO pin is output Chapter 3 – AMI BIOS Setup...

  • Page 104: Legacy Logical Devices Config Uration

    3.5.5 Le gacy Logical Devices Configuration Chapter 3 – AMI BIOS Setup...

  • Page 105: Serial Port 1 Configuration

    3.5.5.1 Se ri al Port 1 Configuration Op tions Summary U s e This Device Disable Enable Optimal Default, Failsafe Default Enable or Disable this Logical Device. Po ssible: Use Automatic Settings Optimal Default, Failsafe Default IO=3F8h; IRQ=4 IO=2F8h; IRQ=3 Allows user to change Device's Resource settings.

  • Page 106: Serial Port 2 Configuration

    3.5.5.2 Se ri al Port 2 Configuration Op tions Summary U s e This Device Disable Enable Optimal Default, Failsafe Default Enable or Disable this Logical Device. Po ssible: Use Automatic Settings Optimal Default, Failsafe Default IO=2F8h; IRQ=3 IO=3F8h; IRQ=4 Allows user to change Device's Resource settings.

  • Page 107: Serial Port 3 Configuration

    3.5.5.3 Se ri al Port 3 Configuration Op tions Summary U s e This Device Disable Enable Optimal Default, Failsafe Default Enable or Disable this Logical Device. Po ssible: Use Automatic Settings Optimal Default, Failsafe Default IO=3E8h; IRQ=11 IO=2E8h; IRQ=11 Allows user to change Device's Resource settings.

  • Page 108: Serial Port 4 Configuration

    3.5.5.4 Se ri al Port 4 Configuration Op tions Summary U s e This Device Disable Enable Optimal Default, Failsafe Default Enable or Disable this Logical Device. Po ssible: Use Automatic Settings Optimal Default, Failsafe Default IO=2E8h; IRQ=11 IO=3E8h; IRQ=11 Allows user to change Device's Resource settings.

  • Page 109: Serial Port Console Redirection

    3.5.6 Se ri al Port Console Redirection Op tions Summary Co nsole Redirection Disabled Optimal Default, Failsafe Default Enabled Console Redirection Enable or Disable. Co nsole Redirection EMS Disabled Optimal Default, Failsafe Default Enabled Console Redirection Enable or Disable. Chapter 3 – AMI BIOS Setup...

  • Page 110: Console Redirection Settings

    3.5.6.1 Console Redirection Settings Op tions Summary Terminal Type VT100 VT100+ VT-UTF8 ANSI Optimal Default, Failsafe Default Emulation: ANSI: Extended ASCII char set. VT100: ASCII char set. VT100+: Extends VT100 to support color, function keys, etc. VT-UTF8: Uses UTF8 encoding to map Unicode chars onto 1 or more bytes.
  • Page 111 Op tions Summary Parity None Optimal Default, Failsafe Default Even Mark Space A parity bit can be sent with the data bits to detect some transmission errors. Even: parity bit is 0 if the num of 1's in the data bits is even. Odd: parity bit is 0 if num of 1's in the data bits is odd.

  • Page 112: Pch-Io Configuration

    3.5.7 PCH-IO Configuration Op tions Summary MiniCard Slot Function SATA Optimal Default, Failsafe Default PCIe Select function enabled for Full size MiniCard Slot (CN10) Chapter 3 – AMI BIOS Setup...

  • Page 113: Setup Submenu: Security

    3.6 Se tup Submenu: Security Change User/Administrator Password Y ou can set an Administrator Password or User Password. An Administrator Password must be set before you can set a User Password. The password will be required during boot up, or when the user enters the Setup utility. A User Password does not provide access to many of the features in the Setup utility.

  • Page 114: Trusted Computing

    3.6.1 Trusted Computing Op tions Summary Security Device Support Disable Enable Optimal Default, Failsafe Default Enables or Disables BIOS support for security device. O.S. will not show Security Device. TCG EFI protocol and INT1A interface will not be available. SHA-1 PCR Bank Disable Enable Optimal Default, Failsafe Default...
  • Page 115 Op tions Summary P latform Hierarchy Disabled Enabled Optimal Default, Failsafe Default Enable or disable Platform Hierarchy St orage Hierarchy Disabled Enabled Optimal Default, Failsafe Default Enable or Disable Storage Hierarchy End orsement Hierarchy Disabled Enabled Optimal Default, Failsafe Default Enable or Disable Endorsement Hierarchy TPM2.0 UEFI Spec Version TCG_1_2...

  • Page 116: Secure Boot

    3.6.2 Se cure Boot Op tions Summary Secure Boot Disabled Optimal Default, Failsafe Default Enabled Secure Boot feature is Active if Secure Boot is Enabled, Platform Key (PK) is enrolled and the System is in User mode. The mode change requires platform reset Secure Boot Mode Custom Optimal Default, Failsafe Default...

  • Page 117: Key Management

    3.6.1.1 Ke y Management Op tions Summary Factory Key Provision Disabled Optimal Default, Failsafe Default Enabled Secure Boot feature is Active if Secure Boot is Enabled, Platform Key (PK) is enrolled and the System is in User mode. The mode change requires platform reset R estore Factory Keys Force System to User Mode.
  • Page 118 Op tions Summary R emove 'UEFI CA' from Device Guard ready system must not list 'Microsoft UEFI CA' Certificate in Authorized Signature database (db) R estore DB defaults Restore DB variable to factory defaults P latform Key(PK) Details Export Update Delete Key Exchange Keys Details...

  • Page 119: Setup Submenu: Boot

    3.7 Se tup Submenu: Boot Op tions Summary Quiet Boot Disabled Enabled Optimal Default, Failsafe Default Enables or disables showing boot logo. N etwork Stack Disabled Optimal Default, Failsafe Default Enabled Enable/Disable UEFI Network Stack Chapter 3 – AMI BIOS Setup...

  • Page 120: Bbs Priorities

    3.7.1 BBS Priorities Chapter 3 – AMI BIOS Setup...

  • Page 121: Setup Submenu: Save & Exit

    3.8 Se tup Submenu: Save & Exit Chapter 3 – AMI BIOS Setup...

  • Page 122: Chapter 4 - Driver Installation

    Chapter 4 Chapter 4 – Driver Installation...

  • Page 123: Driver Download/Installation

    Dri ver Download/Installation Drivers for the GENE-TGU6 can be downloaded from the product page on the AAEON website by following this link: https://www.aaeon.com/en/p/3-and-half-inch-sbc-gene-tgu6 Download the driver(s) you need and follow the steps below to install them . A ud io Driver (Windows 10) Open the folder where you unzipped the A ud io Drivers Run the Set up.exe in the folder...
  • Page 124 L A N Drivers (Windows 10) Open the folder where you unzipped the LA N Drivers Read the ReadMe.txt file before proceeding. Caut ion: Be sure to install the driver package before installing the Intel® PROSet package. Open the W ired_driver_26.3_x64 folder Run the W ired_driver_26.3_x64.exe file in the folder Follow the instructions, drivers will be installed automatically.
  • Page 125 To uch Drivers (Windows 10) Open the folder where you unzipped the P eripheral Drivers Run the Set up.exe file in the folder Follow the instructions Drivers will be installed automatically Peripheral Driver (Linux) Open the folder where you unzipped the P eripheral Drivers Follow the instructions contained within the user guides To uch Drivers (Linux) Touch Drivers can be installed via terminal, or through the graphical UI if...

  • Page 126: Appendix A - I/O Information

    Appendix A Appendix A - I/O Information...

  • Page 127: I/O Address Map

    I/O Address Map Appendix A – I/O Information...

  • Page 128: Memory Address Map

    A.2 Me m or y Address Map Appendix A – I/O Information...
  • Page 129 Appendix A – I/O Information...

  • Page 130: Irq Mapping Chart

    A.3 IRQ Mapping Chart Appendix A – I/O Information...
  • Page 131 Appendix A – I/O Information...

  • Page 132: Appendix B - Mating Connectors And Cables

    Appendix B Appendix B – Mating Connectors and Cables...

  • Page 133: Mating Connectors And Cables

    Mating Connectors and Cables Mat ing Connector Connector A vailable F unction Cab le P/N Lab el Cab le Vendor Mo del no Front Panel JP 1 Flyingway FWAA-1049 LED cable 1709100108 Connector +5Vout 2 Pins for CN 1 PINREX PHR-2 1702150155 Connector...
  • Page 134 Mat ing Connector Connector A vailable F unction Cab le P/N Lab el Cab le Vendor Mo del no Digital I/O CN 17 Neltron 2026B-10 Connector LVDS DF13-30DS-1. CN 18 HIROSE Connector USB Port 50238-01041- USB Wafer CN 21 Aces 170010010D Connector Cable...

This manual is also suitable for:

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