Frequency Synthesizer Circuits - Icom IC-V85 Service Manual

APC (Automatic Power Control) CIRCUIT (RF UNIT)
•
The APC (Automatic Power Control) circuit prevents the
transition of the transmit output power level which is caused
by load mismatching or heat effect, etc.
At the power detector (D32, D33), a portion of the transmit
signal is rectified into DC voltage which is proportional to
the transmit power level.
The rectified voltage is applied to the inverted input terminal
of the operational amplifier (IC26, pin 2). The voltage "T3"
from the D/A converter (IC10, pin 10) is applied to the non-
inverted input terminal as the reference.
• APC CIRCUITS
VCO output
from bufffer-amp (Q74)

4-3 FREQUENCY SYNTHESIZER CIRCUITS

• VCO (RF UNIT)
VCO (Voltage Controlled Oscillator) is a oscillator whose
oscillating frequency is controlled by adding voltage (lock
voltage).
VCO oscillates the both of transmit and 1st LO signals. The
VCO output signals are buffer-amplified by Q74 and Q75.
While receiving, the VCO output is passed through the TX/RX
switch (D4) and the LPF (L29, L38, L59, C102, C435, C437,
C539), then applied to the 1st mixer (Q13) to be mixed with
the received signals to produce the 46.35 MHz 1st IF signal.
While transmitting, the buffer-amplified VCO output is
passed through the TX/RX switch (D3) and applied to the
transmit amplifiers.
• PLL (Phase Locked Loop) CIRCUIT (RF UNIT)
The PLL circuit provides stable oscillation of the transmit
frequency and receive 1st LO frequency. The PLL output
frequency is controlled by the divided ratio (N-data) from the
CPU.
• PLL CIRCUITS
45.9 MHz 2nd LO
signal to the FM IF IC
(IC2, pin 2)
×3
Q81
All manuals and user guides at all-guides.com
TX/RX
Q3 Q2
SW
Drv.
PWR
Pre-drv.
AMP
AMP
AMP
D3
IC26
OP
1
AMP
VCO
Q76, D59−D61
Loop
filter
Programmable
5 Charge
divider
pump
Phase
detector
2
The operational amplifier compares the rectified voltage
and reference voltage "T3," and the difference of the voltage
is output from the operational amplifier pin 1. The output
voltage controls the bias of drive (Q2) and power (Q1)
amplifiers for stable transmit output power.
The change of transmit power is carried out by changing the
reference voltage "T3", and transmit muting (deactivation of
drive and power amplifiers) is carried out by TX switch (Q37)
controlled by "TXC" signal from CPU (LOGIC UNIT; IC8, pin
59).
Power detector
ANT
Q1
SW
LPF
D1
PS5V
2
−
3
+ T3
A portion of VCO output is applied to the PLL IC (IC19, pin 8)
via buffer amplifiers (Q5, Q75). The applied signal is divided
at the pre-scalar and programmable counter according to
the control signals "PLLSTB," "PLLDATA" and "PLLCK" from
the CPU (L; IC8, pins 63, 65 and 66). The divided signal
is phase-compared with the reference frequency signal
from the reference frequency oscillator (X4), at the phase
detector.
The phase difference is output from pin 5 as a pulse type
signal after being passed through the internal charge pump.
The output signal is converted into the DC voltage (lock
voltage) by passing through the loop filter (R445−R448,
C472−C475, C519). The lock voltage is applied to the
variable capacitors (D59 and D60) of VCO (Q76, D59−D61)
and locked to keep the VCO oscillating frequency constant.
If the oscillated signal drifts, its phase changes from that of
the reference frequency, causing a lock voltage change to
compensate for the drift in the VCO oscillating frequency.
Buffer
Q74
Buffer
Q75
Buffer
Q5
PLL IC (IC19 )
8
Prescaler
LPF
9
PLLCK
10
Shift register PLLDATA
11
PLLSTB
1
4 - 3
ANT
LPF
TXC
D3
to transmitter circuits
D4
to 1st mixer (Q13)
PLL control signals
from CPU (LOGIC UNIT; IC8)
15.3 MHz reference signal
from reference frequency osciilator (X4)