Frequency Synthesizer Circuits - Icom IC-80AD Service Manual

APC CIRCUIT (RF UNIT)
The APC (Automatic Power Control) circuit stabilizes
transmit output power to prevent transmit output power level
change which is caused by load mismatching or heat effect,
etc.
TX signal is passed through the power detector (VHF; D59,
60/UHF; D50, 53). The power detector rectifies a portion
of the TX signal and converts it into DC voltage which is in
proportion to the transmit output power. The detected voltage
is applied to the APC controller (IC150B). The TX power
setting voltage "PSET" is applied to another input terminal as
the reference voltage.
• TX AMPLIFIERS AND APC CIRCUIT
D101,102
D 100,850
I C100
TX/RX LO
ATT
SW
AMP
PSET

4-3 FREQUENCY SYNTHESIZER CIRCUITS

VCOs
This transceiver has total of five VCOs; one RX VCO and
RX/TX VCOs on the VCO UNIT, and two RX VCOs on the
MAIN UNIT.
• BC BAND VCO (VCO UNIT; Q1, D1, 3, 5, 6)
The BC BAND VCO generates the 1st LO for BC band
(0.495–75.995 MHz) RX.
• VHF BAND VCO (VCO UNIT; Q51, D51, 54)
The VHF BAND VCO generates the 1st LO for VHF band
(76–173.995 MHz) RX, and also TX signal for the operation
on the VHF band.
• UHF BAND VCO (VCO UNIT; Q101, D101–104)
The UHF BAND VCO generates the LO for UHF band (174–
599.995 MHz) RX, and also TX signal for the operation on
the UHF band.
When receiving 600 MHz and higher signals, the UHF BAND
VCO oscillates 269.175–469.17 MHz 1st LO signals, and the
output signal is doubled by the doubler (MAIN UNIT; Q850,
D851) before being applied to the mixer (MAIN UNIT; IC900).
• FREQUENCY SYNTHESIZER CIRCUITS
RF UNIT
BC BAND: 62.145−131.645 MHz
Q1,2,D1-3,5,6
VCO
VHF BAND:
131.350-235.645 MHz
Q51,52,D51-55
Modulation signals
VCO
UHF BAND:
319.175-538.345 MHz
Q101,102,D100-104
VCO
15.3MHz reference frequency
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Q102 Q101 Q100
UHF TX signal
YGR PWR
DRIVE
AM P AM P AM P
GATE
DSET
CTRL
IC150A VHF TX signal
APC
CTRL
IC150B
Q200
BUFF
Q201
LO
AMP
1st LO signals
(A BAND)
Q202
BUFF LPF
VCO UNIT
IC800
LOOP PLL
FILTER IC
4 - 5
The output voltage is applied to the ATT (D101, 102) to con-
trol the attenuation level, to adjust the input level of the YGR
AMP (Q102) so that the TX output power is stable.
The setting of TX power is carried out by applying voltage
"PSET" to the APC controller (IC150B). The output voltage of
the controller controls the bias of the drive and power AMPs
to reduce/increase the gain of these amplifi ers to set the TX
output power to High, Mid., Low and S-Low.
Q152
L100.101.153
C100-103,192 D150,152,153 D50,53
PWR
BPF
DET
Q153
L102,103
D154-156 D59,60
C106,107
PWR ANT
LPF
DET SW
PLL (VCO AND MAIN UNITS)
The PLL circuit provides stable oscillation for both of the
transmit and 1st LO frequencies. By comparing the fedback
VCO output and the reference frequency signal, the oscillating
frequency is stabilized. The PLL output frequency is controlled
by the serial data including divide ratio from the CPU.
A portion of output signals from each VCO are fedback
to the PLL IC (MAIN UNIT: IC800) via buffers (VCO:
Q200, 202) and LPF. The applied VCO outputs are divided
by the prescaler and programmable divider, then phase-
compared with divided reference frequency from X450
(MAIN). The phase difference is output via the charge pump,
and applied to the VCOs as lock voltage via the loop filter.
When the oscillation frequency drifts, its phase changes
from that of the reference frequency, causing a lock voltage
change to compensate for the drift in the VCO oscillating
frequency.
D 100
D850
TX/RX
SW
ANT
L1-3
L4,C7-9 C1-6
ANT
HPF LPF
SW
L5-7
C10-14
LPF