SECTION 2 INSIDE VIEWS • MAIN UNIT Top view Bottom view TX drive amplifier Power amplifier (Q2: RD01MUS1) (Q1: RD12MVS1) 1st IF mixer Pre-emphasis circuit (Q13: 3SK318YB) (IC3: LMV324IPWR) RF amplifier Antenna switch (Q12: 3SK318YB) (D2: MA77) CPU5 regulator (IC12: S-812C50AMC) FM IF IC (IC2: TA31136FN) IF amplifier...
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SECTION 3 DISASSEMBLY INSTRUCTIONS 1. Removing the chassis panel 2. Removing the MAIN unit. q Remove the knob A and jack cap B . q Remove the Jack seal F. w Unscrew 1 nut C. w Unsolder 4 points G of the shield cover. e Unscrew 2 screws D (2 ×...
SECTION 4 CIRCUIT DESCRIPTION The 1st IF signal from the 1st mixer is passed through the 4-1 RECEIVER CIRCUITS crystal filter (FI1) to suppress unwanted signals, and the 4-1-1 ANTENNA SWITCHING CIRCUIT limiter (D63) and then applied to the 1st IF amplifier (Q14). The antenna switching circuit toggles receive line and transmit line.
4-1-6 SQUELCH CIRCUIT The signals from the pre-emphasis circuit are passed through the analog switch (IC4, pins 3, 4) and LPF (IC3, Squelch circuit mutes AF output signal when no signals are pins 13, 14). The signals from the LPF are passed through received.
4-3-3 RECEIVE LOOP 4-3 PLL CIRCUITS The generated 1st LO signal is applied to the PLL IC (IC19, 4-3-1 GENERAL pin 8) via the buffer-amplifiers (Q5, Q75) and is divided at PLL circuits control the VCO circuit. IC19 is a PLL IC and the prescaler section and the programmable divider section, contains prescaler, programmable counter, programmable then applied to the phase detector section.
4-5 POWER SUPPLY CIRCUITS PORT DESCRIPTION 4-5-1 VOLTAGE LINES NUMBER NAME LINE DESCRIPTION NOIS Input port for "NOIS" signal. The voltage from the attached battery pack. ESDA I/O port for EEPROM (IC7). Common 5 V for the CPU (IC8) converted from the Outputs clock signal for EEPROM ESCK CPU5...
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PORT DESCRIPTION NUMBER NAME PLLSTB Outputs PLL strobe signal. Outputs AF regulator (Q15, Q16) control signal. AFON HIGH : While emitting audio Outputs LPF cut-off frequency control signal to the CTCSS switch (Q38). DUSE LOW : When CTCSS or no signal- ing system is in use.
The level converter circuit (Q305 and Q306) converts communication data level between the CPU (IC204) and the connected transceiver’s CPU. Q301, Q302 and Q303 convert control signals level between the UT-118 and the IC-V82. • UT-118 BLOCK DIAGRAM -"TXD_2" signal to "DMOD" signal...
RF power meter 0.1–20 W/50 Ω • JIG (GND) To [MIC] jack Frequency 68 kΩ counter To [SP] jack 3-conductor 3.5 (d) mm ( 1 /8”) plug (CLONE) IC-V82 • ADJUSTMENT MODE DISPLAY Operating frequency Adjustment item 5 - 1...
5-2 IC-V82 ADJUSTMENT 5-2-1 KEY OPERATION FOR THE ADJUSTMENT • Rotate [VOL] to adjust the value. • Push [D•CLR] key to store the adjustment value and move to next adjustment item. • Push [ ]/[ ] key to move to next adjustment item without changing the value.
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5-2-3 RECEIVE ADJUSTMENT ADJUSTMENT ADJUSTMENT CONDITION OPERATION SENSITIVITY 1 • Connect an SSG to the antenna • Push [D•CLR] key. connector and set as; Frequency : 136.020 MHz Level : 0 dBµ* Modulation : 1 kHz Deviation : ± 3.5 kHz •...
5-3 UT-118 ADJUSTMENT • CONNECTION (BOTTOM VIEW) Power supply 5.0 V DC / 1 A Power supply 8.0 V DC / 1 A J301, Pin 14 Entering adjustment mode • ADJUSTMENT ADJUSTMENT ADJUSTMENT CONDITION OPERATION ENTERING • Connect the pin 14 of J301 to GND to enter the adjustment mode. ADJUSTMENT MODE CODEC...
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SECTION 9 BOARD LAYOUTS MAIN UNIT • TOP VIEW The combination of this page and next page shows the unit layout in the same configuration as the actual P.C. Board. H100 H105 H110 H115 H120 H125 S801 ENCODER BATT ANTENNA EXT.
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• BOTTOM VIEW To Optional unit J301 The combination of this page and previous page shows the unit layout in the same configuration as the actual P.C. Board. H125 H120 H115 H110 H105 H100 MICROPHONE MIC GND 9 - 2...
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