Network Status Indication - Quectel EC21 Series Hardware Design

Figure 28: Reference Design of SGMII Interface with PHY AR8033 Application
To enhance the reliability and availability in customers' applications, please follow the criteria below in
the Ethernet PHY circuit design:
 Keep SGMII data and control signals away from other sensitive circuits/signals such as RF circuits,
analog signals, etc., as well as noisy signals such as clock signals, DC-DC signals, etc.
 Keep the maximum trace length less than 25.4 cm and keep the length difference on the differential
pairs less than 0.5 mm.
The differential impedance of SGMII data trace is 100 Ω ±10%, and the reference ground of the area

should be complete.
 Make sure the trace spacing between SGMII_TX and corresponding SGMII_TX is at least 3 times of
the trace width, and the same to the adjacent signal traces.

3.17. Network Status Indication

The network indication pins can be used to drive network status indication LEDs. The module provides
two pins which are NET_MODE and NET_STATUS. The following tables describe the pin definition and
logic level changes in different network status.
EC21_Series_Hardware_Design
LTE Standard Module Series
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