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Freescale Semiconductor TWR-P1025 Hardware User's Manual

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TWR-P1025 Tower Module
Hardware User Guide
TWR-P1025HUG
Rev. 0, 3/2012

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Summary of Contents for Freescale Semiconductor TWR-P1025

  • Page 1 TWR-P1025 Tower Module Hardware User Guide TWR-P1025HUG Rev. 0, 3/2012...
  • Page 2 Freescale Semiconductor Japan Ltd. or for any other application in which the failure of the Freescale Semiconductor product Headquarters could create a situation where personal injury or death may occur. Should Buyer...

  • Page 3: Table Of Contents

    Local Bus Interface ......................3-8 3.11 UART..........................3-8 3.12 I2C ........................... 3-9 3.13 SPI............................ 3-9 3.14 DDR3 ..........................3-9 3.15 GPIO & Interrupts ......................3-12 Chapter 4 Switch Table P1025 Jumper Table......................4-1 TWR-P1025 Hardware User Guide, Rev. 0 Freescale Semiconductor...
  • Page 4 Input/Output Connectors and Pin Usage Table LED Usage........................5-1 I/O Connectors and Pin Usage Table ................5-1 Chapter 6 Tower Elevator Connections Overview.......................... 6-1 Appendix A Revision History Version Number 0 ......................7-1 TWR-P1025 Hardware User Guide, Rev. 0 Freescale Semiconductor...
  • Page 5 Number Title Number Freescale Tower System......................1-1 Callouts on front side of the TWR-P1025 ................1-3 Callouts on back side of the TWR-P1025................1-3 Power Supply Barrel Connector (J2) Polarity................. 2-1 TWR-P1025 Block Diagram....................3-1 P1025 Clocking Scheme ......................3-3 eTSEC connection to AR8035 PHY ..................
  • Page 6 P1025 GPIO Usage ....................... 3-13 P1025 Jumper Table........................ 4-1 LED Usage Table ........................5-1 I/O Connectors and Pin Usage Table ..................5-1 TWR-P1025 Primary Connector Pinout ................. 6-1 TWR-P1025 Primary Connector Pinout ................. 6-4 TWR-P1025 Hardware User Guide, Rev. 0 Freescale Semiconductor...

  • Page 7: Twr-P1025 Overview

    (MPU) devices. The TWR-P1025 features the QorIQ P1025 dual core processor based on the PowerPC® e500 core architecture. The TWR-P1025 is available as a stand-alone product or can be combined with the Tower Elevator Modules (TWR-ELEV) and other Tower eco-system components to create development platforms for a wide variety of applications.

  • Page 8: Features

    512 MB DDR3@667 MHz • 64 MB Flash • IEEE1588 pinned to header + DAC and VXCO (DNP option) Figure 1-2 Figure 1-3 show the TWR-P1025 with some of the key features. TWR-P1025 Hardware User Guide, Rev. 0 Freescale Semiconductor...

  • Page 9: Callouts On Front Side Of The Twr-P1025

    TWR-P1025 Overview Figure 1-2. Callouts on front side of the TWR-P1025 Figure 1-3. Callouts on back side of the TWR-P1025 TWR-P1025 Hardware User Guide, Rev. 0 Freescale Semiconductor...

  • Page 10: Getting Started

    TWR-P1025 Overview Getting Started Follow the printed Quick Start Guide or the interactive DVD contained in the TWR-P1025 box for recommended get started steps. Reference Documents For more information on the QorIQ family, Tower System, and MPU Modules refer following documents: •...

  • Page 11: Power Requirements

    There are several expansion options on the board that allow external boards to interface to the TWR-P1025, such as the mini PCIe connector, USB ports and elevator expansion. As these plug in cards have variable power requirements as well as numerous population combinations the Power capability of...

  • Page 12: Hardware Description

    Chapter 3 Hardware Description The TWR-P1025 is a Tower Controller Module featuring the P1025-a dual core e500v2 based microprocessor in a 561 TEPBGA package with a maximum core operating frequency of 533MHz. It is intended to be used stand-alone or in the Freescale Tower System. Power is supplied through a 5V barrel connector.

  • Page 13: Clocking

    (also called the platform clock). The CCB clock is used by virtually all of the synchronous system logic, including the L2 cache, and other internal blocks such as the DMA and interrupt controller. The CCB TWR-P1025 Hardware User Guide, Rev. 0 Freescale Semiconductor...

  • Page 14: P1025 Clocking Scheme

    Data transfers are synchronized to the CCB clock internally. Figure 3-2. P1025 Clocking Scheme Table 3-1 Table 3-2 describe the CCB and core platform frequency ratio selection. Table 3-3 describes the DDRCLK input ratio to DDR controller clock ratio. TWR-P1025 Hardware User Guide, Rev. 0 Freescale Semiconductor...

  • Page 15: P1025 Ccb To Sysclk Ratio Selection

    No Default Reserved Table 3-3. P1025 DDR Clock PLL Ratio Reset Configuration e500 Core: CCB Clock Functional Signals Value Name Ratio TSEC_1588_CLK_OUT, cfg_ddr_pll[0:2] TSEC_1588_PULSE_OUT1, TSEC_1588_PULSE_OUT2 No Default 10:1 Reserved Reserved Synchronous mode TWR-P1025 Hardware User Guide, Rev. 0 Freescale Semiconductor...

  • Page 16: System Power

    66.667 66.667 System Power The TWR-P1025 is powered through a barrel connector that provides 5V to the board (and elevators if present). All further operating voltages are generated via onboard regulators. The power supply should be rated at 5V @5A.

  • Page 17: Etsec Connection To Ar8035 Phy

    Input RX data bit RXD2 TSEC1_RXD01 AG22 Input RX data bit RXD1 TSEC1_RXD00 AE24 Input RX data bit RXD0 TSEC1_RX_DV AE25 Input RX data RX_CTL valid/error TSEC1_RX_CLK AE26 Input RX clock RX_CLK TWR-P1025 Hardware User Guide, Rev. 0 Freescale Semiconductor...

  • Page 18: Usb

    The P1025 features a USB full-speed/low-speed OTG/Host/Device controller. The controller connects to the USB3300 USB PHY with the USB D+ and D- signals from the USB3300 routed to a four-port USB TWR-P1025 Hardware User Guide, Rev. 0 Freescale Semiconductor...

  • Page 19: Micro Secure Digital Card Slot (Micro Sdhc)

    Micro Secure Digital Card Slot (micro SDHC) A micro Secure Digital (SD) card slot is available on the TWR-P1025 connected to the SD Host Controller (SDHC) signals of the P1025. Refer to Table 13 "I/O Connectors and Pin Usage Table" for the SDHC signal connection details.

  • Page 20: Spi

    Every DDR3 signal can be considered to be a member of one of four separate groups. Each group has unique rules in terms of signal connection and signal routing. The four groups and connectivity between controller and Memory are shown in Table 3-9. TWR-P1025 Hardware User Guide, Rev. 0 Freescale Semiconductor...

  • Page 21: Ddr3 Signals

    UDQS+/- Data Strobes/comple ment MDM0 Data Mask MDM1 Data Mask MDM2 Data Mask MDM3 Data Mask MDQ[7:0] DQ[7:0] Data Bus MDQ[15:8] DQ[15:8] Data Bus MDQ[23:16] DQ[7:0] Data Bus MDQ[31:24] DQ[15:8] Data Bus TWR-P1025 Hardware User Guide, Rev. 0 Freescale Semiconductor...
  • Page 22 ${DDR_CONT_GROUP}TIMING_CFG_1 = 0x5c5b6544 # TIMING_CFG_2 #reg ${DDR_CONT_GROUP}TIMING_CFG_2 = 0x0fa8c8cf reg ${DDR_CONT_GROUP}TIMING_CFG_2 = 0x0fa880de # TIMING_CFG_3 #reg ${DDR_CONT_GROUP}TIMING_CFG_3 = 0x00020000 reg ${DDR_CONT_GROUP}TIMING_CFG_3 = 0x00020000 # DDR_SDRAM_CFG_2 #reg ${DDR_CONT_GROUP}DDR_SDRAM_CFG_2 = 0x04401040 reg ${DDR_CONT_GROUP}DDR_SDRAM_CFG_2 = 0x04401050 TWR-P1025 Hardware User Guide, Rev. 0 Freescale Semiconductor...

  • Page 23: Gpio & Interrupts

    ${DDR_CONT_GROUP}DDRCDR_2 = 0x00000000 #delay before enable wait 500 # DDR_SDRAM_CFG reg ${DDR_CONT_GROUP}DDR_SDRAM_CFG = 0xc70c0000 #wait for DRAM data initialization wait 2000 3.15 GPIO & Interrupts Table 3-10 lists external interrupt sources of P1025. TWR-P1025 Hardware User Guide, Rev. 0 Freescale Semiconductor...

  • Page 24: P1025 Interrupt Usage

    Secondary elevator GPIO27/J4.13 GPIO_EXPAND9 Secondary elevator GPIO28/J4.15 GPIO_EXPAND10 Secondary elevator GPIO17/J4.17 GPIO_EXPAND11 Secondary elevator GPIO26/J4.16 GPIO_EXPAND12 Primary elevator GPIO4/J4.18 GPIO_EXPAND13 Primary elevator GPIO6/J4.20 GPIO_EXPAND14 Unused/CPLD GPIO_EXPAND15 Unused/CPLD CE_PB27 LED D2 CE_PB31 LED D3 TWR-P1025 Hardware User Guide, Rev. 0 Freescale Semiconductor...

  • Page 25: Switch Table

    Chapter 4 Switch Table P1025 Jumper Table There are several switches on the TWR-P1025 that provide configuration selection and signal isolation (Table 4-1). The default switch settings are shown in red. Table 4-1. P1025 Jumper Table Feature Settings Comments [OFF=1 ON=0] S1.1...
  • Page 26 [OFF=1 ON=0] S1.9 ETH_TDM_SEL Ethernet1 clock routed to P1025 through CPLD TDM Clock routed to P1025 through CPLD PROFIBUS_MODE_SEL S1.10 normal mode - RTS inverted debug mode – RTS connected to CTS TWR-P1025 Hardware User Guide, Rev. 0 Freescale Semiconductor...

  • Page 27: Input/Output Connectors And Pin Usage Table

    Input/Output Connectors and Pin Usage Table LED Usage Table 5-1 provides details on which P1025 pins are used to communicate with the LEDs, switches, and other I/O interfaces onboard the TWR-P1025. Table 5-1. LED Usage Table Description Color LED On...
  • Page 28 Test Reset CPU_TCLK J3.5 Test CLK +3.3V J3.6 Power CPU_TMS J3.7 Test Mode Select CKSTP_IN_N J3.8 Checkstop In J3.9 J3.10 COP_SRST_N J3.11 COP Soft Reset J3.12 Ground COP_HRST_N J3.13 COP Hard Reset J3.14 TWR-P1025 Hardware User Guide, Rev. 0 Freescale Semiconductor...
  • Page 29 UCC7 CD SER3_CTS_B J4.12 UCC3 CTS_B GPIO_EXPAND8 J4.13 GPIO SER3_CD J4.14 UCC3 CD GPIO_EXPAND9 J4.15 GPIO GPIO_EXPAND11 J4.16 GPIO GPIO_EXPAND10 J4.17 GPIO GPIO_EXPAND12 J4.18 GPIO +5V0 J4.19 5V Power GPIO_EXPAND13 J4.20 GPIO TWR-P1025 Hardware User Guide, Rev. 0 Freescale Semiconductor...
  • Page 30 Reserved P2.4 Ground P2.5 Reserved +1.5V P2.6 Power CLKREQ# P2.7 P2.8 Reserved P2.9 Ground P2.10 Reserved REFCLK- P2.11 MPCIE_CLK_N P2.12 Reserved REFCLK+ P2.13 MPCIE_CLK_P P2.14 Reserved P2.15 Ground P2.16 Reserved P2.17 Reserved TWR-P1025 Hardware User Guide, Rev. 0 Freescale Semiconductor...
  • Page 31 P2.36 USB2_DM P2.37 Reserved USB_D+ P2.38 USB2_DP P2.39 Reserved P2.40 Ground P2.41 Reserved LED_WWAN P2.42 P2.43 Reserved LED_WLAN P2.44 P2.45 Reserved LED_WPAN P2.46 P2.47 Reserved +1.5V P2.48 Power P2.49 Reserved P2.50 Ground TWR-P1025 Hardware User Guide, Rev. 0 Freescale Semiconductor...
  • Page 32 Input/Output Connectors and Pin Usage Table Table 5-2. I/O Connectors and Pin Usage Table (continued) Feature Connection Port Pin Pin Function P2.51 Reserved +3.3V P2.52 Power TWR-P1025 Hardware User Guide, Rev. 0 Freescale Semiconductor...

  • Page 33: Tower Elevator Connections

    Tower system. The Primary Connector (comprised of sides A and B) is utilized by the TWR-P1025 while the Secondary Connector (comprised of sides C and D) makes connections to the the SER3 & 7 Serial ports as well as ENET5 RMII and three SERDES lanes. Table 14 provides the pinout for the Primary Connector.
  • Page 34 Tower Elevator Connections Table 6-1. TWR-P1025 Primary Connector Pinout (continued) Pin# Side B Pin# Side A ETH_TXEN ENET1_TXE ETH_RXCLK ENET1_RXCLK ETH_TXER ENET1_TXE ETH_RXDV ENET1_RX_DV ETH_TXD3 ENET1_TXD3 ETH_RXD3 ENET1_RXD3 ETH_TXD2 ENET1_TXD2 ETH_RXD2 ENET1_RXD2 ETH_TXD1 ENET1_TXD1 ETH_RXD1 ENET1_RXD1 ETH_TXD0 ENET1_TXD0 ETH_RXD0 ENET1_RXD0...
  • Page 35 Tower Elevator Connections Table 6-1. TWR-P1025 Primary Connector Pinout (continued) Pin# Side B Pin# Side A SPI0_MISO SPI0_MISO TXD1 SPI0_MOSI SPI0_MOSI SPI0_CS0_b ELEV_SPI0_ VDDA CS0_b SPI0_CS1_b ELEV_SPI0_ VREFA1 CS1_b SPI0_CLK SPI0_CLK VREFA2 Ground Ground SCL1 I2C2_SCL GPIO14 GPIO_EXPAND5 SDA1 I2C2_SDA...

  • Page 36: Twr-P1025 Primary Connector Pinout

    Tower Elevator Connections Table 6-1. TWR-P1025 Primary Connector Pinout (continued) Pin# Side B Pin# Side A EBI_OE_b ELEV_OE EBI_AD8 ELEV_LAD8 EBI_D7 ELEV_D7 EBI_AD7 ELEV_LAD7 EBI_D6 ELEV_D6 EBI_AD6 ELEV_LAD6 EBI_D5 ELEV_D5 EBI_AD5 ELEV_LAD5 EBI_D4 ELEV_D4 EBI_AD4 ELEV_LAD4 EBI_D3 ELEV_D3 EBI_AD3 ELEV_LAD3...
  • Page 37 Tower Elevator Connections Table 6-2. TWR-P1025 Primary Connector Pinout (continued) Pin# Side B Pin# Side A GPIO18 ETH_RXDV ENET5_RX_DV GPIO19 / SDHC_D4 GPIO27 / GPIO_EXPAND8 SDHC_D6 GPIO20 / SDHC_D5 GPIO28 / GPIO_EXPAND9 SDHC_D7 ETH_TXD1 ENET5_TX ETH_RXD1 ENET5_RXD1 (LWE1_b) ETH_TXD0 ENET5_TX...
  • Page 38 Tower Elevator Connections Table 6-2. TWR-P1025 Primary Connector Pinout (continued) Pin# Side B Pin# Side A GPIO21 GPIO_EXPA GPIO30 / SER7_CD ND12 UART3_DC 3.3V 3.3V Power 3.3V 3.3V Power PWM15 PWM11 PWM14 PWM10 PWM13 PWM9 PWM12 PWM8 CAN2_RX UART2_RX SER3_RXD0...
  • Page 39 Tower Elevator Connections Table 6-2. TWR-P1025 Primary Connector Pinout (continued) Pin# Side B Pin# Side A IRQ_O / SPI2_CS3_b IRQ_G LCD_D10 / LCD_P10 IRQ_N IRQ_F LCD_D11 / LCD_P11 IRQ_M IRQ_E I2S1_DIN_S IRQ_L IRQ_D I2S1_DIN_ IRQ_K IRQ_C I2S1_DIN1 IRQ_J IRQ_B I2S1_DOUT...
  • Page 40 Tower Elevator Connections Table 6-2. TWR-P1025 Primary Connector Pinout (continued) Pin# Side B Pin# Side A EBI_AD26 / LCD_P48 / ELEV_SD_ EBI_TS_b / SD_GND SD_RX_2 RX3_P LCD_P34 / SD_GND EBI_AD27 / LCD_P49 / ELEV_SD_ EBI_TBST_ SD_GND SD_RXb_2 RX3_N b / LCD_P35...

  • Page 41: Appendix A Revision History

    Appendix A Revision History This appendix provides a list of the major differences between current TWR-P1025 hardware user guide and its previous revisions. Version Number 0 This is initial version of the TWR-P1025 Hardware User Guide. TWR-P1025 Hardware User Guide, Rev. 0...

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