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Freescale Semiconductor MCF5441X User Manual

Tower module
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MCF5441X Tower Module
User Manual
Rev. 1.1
Freescale Semiconductor Inc.
Microcontroller Solutions Group

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Summary of Contents for Freescale Semiconductor MCF5441X

  • Page 1 MCF5441X Tower Module User Manual Rev. 1.1 Freescale Semiconductor Inc. Microcontroller Solutions Group...

  • Page 2: Table Of Contents

    4.13.1 Default Configuration (J5: 3-4 and 1-2 = ON:ON) ....................15 4.13.2 Parallel Configuration (J5: 3-4 and 1-2 = ON:OFF)................... 16 4.13.3 Serial Configuration (J5 OFF:OFF) ........................17 4.14 J ..............................20 UMPERS WITCHES 4.15 C ................................21 RACE MCF5441X Tower Module Hardware Specification Page 2 of 31...

  • Page 3: Purpose

    Cut/Trace Pads 3 Overview 3.1 MCF5441x Overview The following is a brief summary of the functional blocks in the MCF5441x superset device. Version 4 ColdFire Core with MMU and EMAC o CPU @250 MHz 16 KBytes instruction cache and 16 KBytes data cache...
  • Page 4 Random number generator Synchronous serial interface (SSI) Four 32-bit timers with DMA support Four DMA-supported serial peripheral interface (DSPI) Ten UARTs Six I C bus interface 12-bit ADC A multi-channel PWM Two DACs MCF5441X Tower Module Hardware Specification Page 4 of 31...

  • Page 5: Twr-Mcf5441X Overview

    3.2 TWR-MCF5441X Overview The TWR-MCF5441X provides hardware to evaluate as many of the configurations of the MCF5441x family as possible. The TWR-MCF5441X features: Tower compatible processor board MCF54418 in a 256 MAPBGA package DDR2 SDRAM (128 MByte) A NAND Flash memory device (256MByte)

  • Page 6: Hardware Specification

    This section provides specification details for the TWR-MCF5441X board. 4.1 Microcontroller The microcontroller on the TWR-MCF5441X will be a member of the highly-integrated 32-bit microprocessor family based on the Coldfire V4m with MMU, EMAC, and CAU units. MCF5441X Tower Module Hardware Specification...

  • Page 7: Clocking

    SDRAM bus speed is set at 250 MHz to generate a 500 MHz data rate. The system bus clock is set at 125MHz. All clock speeds such as CPU, SYSTEM, SDHC, USB and NAND can be programmable to desire frequency with software modification and jumpers. MCF5441X Tower Module Hardware Specification Page 7 of 31...

  • Page 8: System Power

    TWR-MCF5441X provides two debug interfaces – a standard BDM and an Open Source BDM (OSBDM). 4.4.1 Stardard BDM The primary debug port on the TWR-MCF5441X is referred to as the background debug module or BDM. The standard 26-pin BDM header (J11) is provided on the TWR-M5441X for attachment of an external BDM control interface.
  • Page 9 PSTCLK/OSBDM Table 2 - BDM Headers The MCF5441x also features IEEE 1149.1 Test Access Port (JTAG) test logic that can be used for boundary-scan testability. The access pins for JTAG are multiplexed over the BDM control signals and are available on J11.

  • Page 10: Osbdm Bootloader Mode

    UART0 and UART4. Two 2x5 pin headers are provided allowing access to the RS232 interfaces - J1 (UART0) and J3 (UART4). A 2x5 adaptor to Female DB9 serial cable must be used in order to establish serial communication. MCF5441X Tower Module Hardware Specification Page 10 of 31...

  • Page 11: Sdram Interface

    Table 6 - J1 & J3 4.6 SDRAM Interface The MCF5441x is capable of supporting 256MB DDR2-500 1.8V SDRAM at 250MHz SDRAM Clock. To reduce cost, the TWR-M54418 uses an 8-bit memory bus to interface to 128MB Micron MT47H128M8 DDR2 SDRAM.

  • Page 12: Potentiometer

    For more details regarding the Cut-Trace pad options and the pad numbering refer to the Cut-Trace Pad section of this document. 4.9 Potentiometer The TWR-MCF5441X includes an on-board potentiometer to allow the user to simulate an analog input. MCF5441X Tower Module Hardware Specification...

  • Page 13: Temperature Sensor

    TWR-M54418 uses 1-wire interface (OWIO) to interact with temperature sensor Maxim DS18B20 digital thermometer. The sensor device is powered from TWR-MCF5441X’s 3.3V power circuit. The Parasite-Powered method (where the power source is from data bus) is not used in this platform.

  • Page 14: Reset Configuration

    For more details regarding the Cut-Trace pad options and the pad numbering refer to the Cut-Trace Pad section of this document. 4.13 Reset Configuration The TWR-MCF5441X has three boot mode options: Boot with default configuration constants specified in the RCON register Boot with NAND/NOR with configuration data specified by the Flexbus FB_AD[7:0] pins Boot with configuration data obtained from an external SPI memory through the serial boot facility.

  • Page 15: Default Configuration (J5: 3-4 And 1-2 = On:on)

    4.13.1 Default Configuration (J5: 3-4 and 1-2 = ON:ON) If the BOOTMOD pins are 00 during reset, the MCF5441x’s RCON register determines the chip configuration after reset, regardless of the states of the external data pins. The RCON register specifies...

  • Page 16: Parallel Configuration (J5: 3-4 And 1-2 = On:off)

    FB_AD[7:0] pins. On the TWR-MCF5441X, the FB_AD[7:0] pins are actively driven by two 4-bit buffers enabled when the MCF5441x RSTOUT signal is asserted. The values driven by the buffer are set by the SW1 DIP switch settings. For SW1, a value of 0 implies that the dip is switched “On”.

  • Page 17: Serial Configuration (J5 Off:off)

    SPI memory to allow for module configuration. See Table below. BYTE Address Data Contents {0000, BLDIV[3:0]} BLL[7:0] BLL[15:8] RCON[7:0] RCON[15:8] RCON[23:16] RCON[31:24] Table 11 - Serial Boot Facility 7-BYTE Header MCF5441X Tower Module Hardware Specification Page 17 of 31...
  • Page 18 FlexBus Runs at Fsys/2 FlexBus Runs at Fsys/4 SBF_RCON[14:10] NFC Clock Frequency (PLL_DR[OUTDIV5]) SBF_RCON[9:5] Internal Bus Clock Frequency (PLL_DR[OUTDIV5]) SBF_RCON[4:0] Core Bus Clock Frequency (PLL_DR[OUTDIV5]) Table 12 - Serial Boot Facility RCON Bit Definitions MCF5441X Tower Module Hardware Specification Page 18 of 31...
  • Page 19 Instead, it will depend on the SBF_RCON bit 29 to determine whether the code will continue to load at address 0 either from FlexBus or NAND flash. Table 13 - Easy Configurable Serial RCON MCF5441X Tower Module Hardware Specification Page 19 of 31...

  • Page 20: Jumpers, Switches

    4.14 Jumpers, Switches The TWR-MCF5441X implements a number of configuration jumpers, switches and headers. Refer to this section for a quick overview of each. For more details refer to the specific section related to the functionality of the specific jumper, switch, or header.

  • Page 21: Cut/Trace Pads

    4.15 Cut/Trace Pads Cut/Trace pads have been implemented on the TWR-MCF5441X in place of configuration jumpers to ease board area constraints. Physical Implementation Schematic View Default Source Default Sink Alternate Sink Alternate Source / Alternate Sink Trace/Cut Pad Default Connection...
  • Page 22 The TWR-MCF5441X implements the following Cut-Trace pads: Cut- Function Primary Setting Alternative Setting Trace Pads UART5 TXD 1-2: Connects TXD to TWR-ELEV 1-3: Connects TXD to JM60 UART5 RXD 1-2: Connects RXD to TWR-ELEV 1-3: Connects RXD to JM60 ADC_0...
  • Page 23 PH6/SSI0_TXD Power Ground ADC_IN3/DAC0_OUT ADC_IN2 ADC_IN1 ADC_IN0 Power Ground DAC0 TMR1 Timer PD1/RGPIO/T2IN/T2OUT TMR0 Timer PD0/RGPIO/T1IN/T1OUT GPIO6 GPIO PB5/GPIO 3.3V Power 3.3V Power PWM3 PF1/PWM_B1 PWM2 PF2/PWM_A1 PWM1 PG6/PWM_B0 PWM0 PG5/PWM_A0 MCF5441X Tower Module Hardware Specification Page 23 of 31...
  • Page 24 FB_AD8 FB_AD7 Flexbus FB_AD7 FB_AD6 Flexbus FB_AD6 FB_AD5 Flexbus FB_AD5 FB_AD4 Flexbus FB_AD4 FB_AD3 Flexbus FB_AD3 FB_AD2 Flexbus FB_AD2 FB_AD1 Flexbus FB_AD1 FB_AD0 Flexbus FB_AD0 Power Ground 3.3V Power 3.3V Power MCF5441X Tower Module Hardware Specification Page 24 of 31...
  • Page 25 Clock RMII_REF_CLK CLKOUT1 Clock Power Ground ADC_IN6 ADC_IN5 ADC_IN4 Power Ground DAC1 TMR3 Timer TMR2 Timer GPIO4 GPIO PB6/GPIO 3.3V Power 3.3V Power PWM7 PWM6 PWM5 PG7/PWM_B2 PWM4 PF0/PWM_A2 CANRX PC7/CAN1_RX MCF5441X Tower Module Hardware Specification Page 25 of 31...
  • Page 26 PA6/FB_OE/NFC_RE FB_D7 Flexbus FB_AD31 FB_D6 Flexbus FB_AD30 FB_D5 Flexbus FB_AD29 FB_D4 Flexbus FB_AD28 FB_D3 Flexbus FB_AD27 FB_D2 Flexbus FB_AD26 FB_D1 Flexbus FB_AD25 FB_D0 Flexbus FB_AD24 Power Ground 3.3V Power 3.3V Power MCF5441X Tower Module Hardware Specification Page 26 of 31...
  • Page 27 ULPI ULPI_DATA3 USB_DATA4 ULPI ULPI_DATA4 Power Ground AN11 AN10 Power Ground GPIO GPIO TMR9 Timer TMR8 Timer GPIO GPIO 3.3V Power 3.3V Power PWM11 PWM10 PWM9 PWM8 RXD2 UART 2 PE4/UART2_RXD MCF5441X Tower Module Hardware Specification Page 27 of 31...
  • Page 28 FB_CS3 / LCD38 Flexbus / Display FB_CS2 / LCD39 Flexbus / Display FB_CS1 / LCD40 Flexbus / Display GPIO / LCD41 GPIO LCD_D23 / LCD23 Display Power Ground 3.3V Power 3.3V Power MCF5441X Tower Module Hardware Specification Page 28 of 31...
  • Page 29 LCD_HSYNC / LCD24 Display LCD_VSYNC / LCD25 Display AN13 AN12 Power Ground LCD_CLK / LCD26 Display TMR11 Timer TMR10 Timer GPIO GPIO 3.3V Power 3.3V Power PWM15 PWM14 PWM13 PWM12 CANRX1 MCF5441X Tower Module Hardware Specification Page 29 of 31...
  • Page 30 FB_AD30 / LCD52 Flexbus / Display FB_AD30 FB_AD31 / LCD53 Flexbus / Display FB_AD31 LCD_D20 / LCD20 Display LCD_D21 / LCD21 Display LCD_D22 / LCD22 Display Power Ground 3.3V Power 3.3V Power MCF5441X Tower Module Hardware Specification Page 30 of 31...
  • Page 31 Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2008. All rights reserved. MCF5441X Tower Module Hardware Specification Page 31 of 31...

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