Plunger Driver Circuit - Epson DFX-5000+ Service Manual

Operating Principles

Plunger Driver Circuit

Figure 2-30 shows a block diagram ofthe plunger driver circuit, and Table 2-9
provides the plunger switching pattern. The plunger is driven using three
switching patterns. Gate array general purpose ports PLP and PLN output the
plunger coil drive signals. The CPU latches the switching data in the gate array.
When the PNP port ofthe gate array turns off switching transistor Q19, transistor
Q17 is turned on and the supply voltage (VP) flows into the plunger coil. When
switching transistor Q19 is turned on, transistor Q17 is turned offand the hold
voltage (+5 V) flows into the plunger coil using general purpose port PLN of the
gate array.
Suspension Roller Status
2-42
Figure 2-30. Plunger Driver Circuit
Table 2-10. Plunger Switching Pattern
Q27
Q 1 7