Quectel UC20 Hardware Design page 46

In primary mode, the data is sampled on the falling edge of the PCM_CLK and transmitted on the rising
edge; the PCM_SYNC falling edge represents the MSB. In this mode, PCM_CLK supports 128, 256, 512,
1024, 2048 and 4096kHz for different speech codec.
In auxiliary mode, the data is sampled on the falling edge of the PCM_CLK and transmitted on the rising
edge; while the PCM_SYNC rising edge represents the MSB. In this mode, PCM interface operates with a
128kHz PCM_CLK and an 8kHz, 50% duty cycle PCM_SYNC only.
UC20 supports 8-bit A-law and μ-law, and also 16-bit linear data formats. The following figures show the
primary mode's timing relationship with 8kHz PCM_SYNC and 2048kHz PCM_CLK and auxiliary mode's
timing relationship with 8kHz PCM_SYNC and 128kHz PCM_CLK.
UC20_Hardware_Design
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PCM_CLK
1
PCM_SYNC
MSB
PCM_OUT
MSB
PCM_IN
Figure 26: Primary Mode Timing
PCM_CLK 1 2
PCM_SYNC
MSB
PCM_OUT
MSB
PCM_IN
Figure 27: Auxiliary Mode Timing
Confidential / Released
125us
2 255
LSB
LSB
125us
15
UMTS/HSPA Module Series
UC20 Hardware Design
256
MSB
MSB
16
LSB
LSB
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