Quectel UC20 Hardware Design page 40

VDD_EXT
DCD
CTS
RTS
DTR
TXD
RXD
Please visit http://www.ti.com for more information.
Another example with transistor translation circuit is shown as below. The construction of dotted line can
refer to the construction of solid line. Please pay attention to direction of connection. Input dotted line of
module should refer to input solid line of the module. Output dotted line of module should refer to output
solid line of the module.
MCU/ARM
The following figure is an example of connection between UC20 and PC. A voltage level translator and a
RS-232 level translator chip must be inserted between module and PC, since these two UART interfaces
do not support the RS-232 level, while support the 1.8V CMOS level only.
UC20_Hardware_Design
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0.1uF
RI
51K
Figure 19: Reference Circuit with Translator Chip
VDD_EXT
/TXD
/RXD
4.7K
VCC_MCU
/RTS
/CTS
GPIO
EINT
GPIO
GND
Figure 20: Reference Circuit with Transistor Circuit
VCCA VCCB
OE GND
A1
B1
A2 B2
Translator
A3 B3
A4 B4
A5 B5
A6 B6
A7 B7
A8 B8
4.7K
VDD_EXT
1nF
4.7K
1nF
VDD_EXT
4.7K
Confidential / Released
UMTS/HSPA Module Series
UC20 Hardware Design
VDD_3.3V
0.1uF
RI_3.3V
DCD_3.3V
CTS_3.3V
RTS_3.3V
DTR_3.3V
TXD_3.3V
RXD_3.3V
51K
Module
RXD
TXD
RTS
CTS
DTR
RI
DCD
GND
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