Quectel UC20 Hardware Design page 39

RTS
DTR
TXD
RXD
Table 10: Pin Definition of the Debug UART Interface
Pin Name
DBG_TXD
DBG_RXD
The logic levels are described in the following table.
Table 11: Logic Levels of Digital I/O
Parameter
V
IL
V
IH
V
OL
V
OH
UC20 provides 1.8V UART interface. A level translator should be used if your application is equipped with
a 3.3V UART interface. A level translator TXS0108PWR provided by Texas Instrument is recommended.
The following figure shows the reference design.
UC20_Hardware_Design
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65 DI
66 DI
67 DO
68 DI
Pin No. I/O
12 DO
11 DI
Min
-0.3
1.2
0
1.35
Request to send.
Data terminal ready.
Transmit data.
Receive data.
Description
Transmit data.
Receive data.
Max
0.6
2.0
0.45
1.8
Confidential / Released
UMTS/HSPA Module Series
UC20 Hardware Design
1.8V power domain.
1.8V power domain.
1.8V power domain.
1.8V power domain.
Comment
1.8V power domain.
1.8V power domain.
Unit
V
V
V
V
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