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S1D16400 Series
AC Characteristics
Input timing characteristics
FR
LP
XSCL
D0 to D3
EI01,2
(IN)
XSCL cycle
XSCL HIGH level pulse duration
XSCL LOW level pulse duration
Data setup time
Data hold time
XSCL → LP rise time
LP → XSCL fall time
LP HIGH level pulse duration
FR delay permissible time
EIO setup time
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XSCL cycle
XSCL HIGH level pulse duration
XSCL LOW level pulse duration
Data setup time
Data hold time
XSCL → LP rise time
LP → XSCL fall time
LP HIGH level pulse duration
FR delay permissible time
EIO setup time
*1 6.5MHz equivalence
*2 7.5MHz equivalence
t
*3
specifies the time when LP is HIGH and, at the same time, XSCL is LOW.
wLH
2–10
t
LD
t
t
DS
DH
Items
Items
t
t
WLH
DF
t
LH
Symbols
Conditions
t
C
t
WCH
t
WCL
t
DS
t
DH
t
LD
t
LH
t
*3
WLH
t
DF
t
SUE
Symbols
Conditions
V
=–2.7V
SS
t
C
V
=–3.0V
SS
t
WCH
t
WCL
t
DS
t
DH
t
LD
V
=–2.7V
SS
t
LH
V
=–3.0V
SS
V
=–2.7V
SS
t
WLH
V
=–3.0V
SS
t
DF
V
=–2.7V
SS
t
SUE
V
=–3.0V
SS
EPSON
t
C
t
t
WCH
WCL
t
SUE
V
=–5.0V±0.5V, Ta=–40 ~ 85°C
SS
Min.
Max.
100
30
30
30
20
0
40
40
–900
+900
35
V
=–4.5V ~ 2.7V, Ta=–40 ~ 85°C
SS
Min.
Max.
*1
153
*2
133
50
50
50
30
0
75
65
75
*3
65
*3
–900
+900
50
40
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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