Texas Instruments TPS65033-Q1 Series User Manual

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User's Guide
TPS650330-Q1 EVM User's Guide
The TPS650330-Q1 EVM is an evaluation board for the TPS65033x-Q1 Power Management Integrated Circuits
(PMICs). The EVM includes an onboard USB-to-I
inputs and outputs, and test points for common measurements.
1 Introduction.............................................................................................................................................................................3
2 Requirements..........................................................................................................................................................................3
3 Operation Instructions...........................................................................................................................................................
4 EVM Configurations................................................................................................................................................................6
5 Test Points...............................................................................................................................................................................7
6 Graphical User Interface........................................................................................................................................................
7 Typical Performance Plots...................................................................................................................................................
8 TPS650330-Q1 EVM Schematic...........................................................................................................................................
9 TPS650330-Q1 EVM PCB
10 TPS650330-Q1 EVM Bill of Materials................................................................................................................................
11 TPS650330-Q1 Silicon Revision Changes........................................................................................................................
12 Revision History.................................................................................................................................................................
Figure 4-1. TPS650330-Q1 EVM Top View.................................................................................................................................
Figure 5-1. TPS650330-Q1 EVM Test Point Locations...............................................................................................................
Figure 6-1. TPS650330-Q1 EVM Debugging Flow
Figure 6-2. Opening Serial Port
Figure 6-3. Selecting an Alternate
Figure 6-4. TPS6503xx-Q1 GUI Home
Figure 6-5. TPS6503xx-Q1 GUI Block Diagram
Figure 6-6. Register Page Interfaces.........................................................................................................................................12
Figure 6-7. TPS6503xx-Q1 GUI Device Configuration
Figure 6-8. Device Selection for Generating NVM
Figure 6-9. Example Settings
Figure 6-10. Sequencing Overview
Figure 6-11. Sequencing Overview Including GPIO..................................................................................................................
Figure 6-12. GUI Generated Timing
Figure 6-13. TPS6503xx-Q1 GUI Re-Program PMIC Page......................................................................................................
Figure 6-14. GUI Configuration CRC
Figure 7-1. TPS650330-Q1 Default Power Up Sequence.........................................................................................................
Figure 7-2. TPS650330-Q1 Default Power Down Sequence....................................................................................................
Figure 8-1. TPS650330-Q1
Figure 8-2. MSP432E401Y Schematic......................................................................................................................................
Figure 9-1. Top Layer.................................................................................................................................................................23
Figure 9-2. Mid-Layer 1.............................................................................................................................................................
Figure 9-3. Mid-Layer 2.............................................................................................................................................................
Figure 9-4. Mid-Layer 3.............................................................................................................................................................
Figure 9-5. Mid-Layer 4.............................................................................................................................................................
Figure 9-6. Bottom Layer (Mirrored)..........................................................................................................................................
Table 3-1. Adapter Power Source
Table 3-2. Dedicated LDO Supply for Adapter (J19)...................................................................................................................
Table 3-3. Adapter PMIC Connections........................................................................................................................................
SLVUBI2A - JULY 2018 - REVISED OCTOBER 2020
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ABSTRACT
2
C adapter, power terminals and jumpers for all DC regulator

Table of Contents

Layers.........................................................................................................................................23
List of Figures
Chart............................................................................................................9
Options....................................................................................................................................10
Port......................................................................................................................................10
Screen..........................................................................................................................11
Page...............................................................................................................12
Page.....................................................................................................13
Settings.......................................................................................................14
Output.........................................................................................................................................14
Tab.....................................................................................................................................15
Diagram............................................................................................................................16
Script...............................................................................................................................17
Schematic......................................................................................................................................21
List of Tables
(J18).......................................................................................................................................3
Copyright © 2020 Texas Instruments Incorporated
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