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NXP Semiconductors freescale M5251C3 User Manual

NXP Semiconductors freescale M5251C3 User Manual

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M5251C3 Evaluation Board
Users Guide
Document Number: M5251C3UG
Rev. 0
05/2006

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Summary of Contents for NXP Semiconductors freescale M5251C3

  • Page 1 M5251C3 Evaluation Board Users Guide Document Number: M5251C3UG Rev. 0 05/2006...
  • Page 2 How to Reach Us: Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products. There are no express or implied copyright licenses granted Home Page: hereunder to design or fabricate any integrated circuits or integrated circuits based on the information www.freescale.com in this document.

  • Page 3: Table Of Contents

    Contents Chapter 1 M5251C3 Evaluation Board General Hardware Description ..........1-1 System Memory .
  • Page 4 2.4.14 IRM (Internal Register Modify) ..........2-13 2.4.15 HELP (Help) .
  • Page 5 3.2.4 FlexCAN Modules ............3-6 3.2.5 USB 2.0 OTG Module .
  • Page 6 M5251C3 Evaluation Board Users Guide, Rev. 0 Freescale Semiconductor...

  • Page 7: M5251C3 Evaluation Board

    Chapter 1 M5251C3 Evaluation Board The 5251 is a versatile single-board computer based on the MCF5251 ColdFire® Processor. It may be used as a powerful microprocessor based controller in a variety of applications. It serves as a complete microcomputer system for reference design, development/evaluation, training, and educational use. The user need only connect an RS-232 compatible terminal (or a personal computer with terminal emulation software) and a power supply to have a fully functional system.

  • Page 8: System Memory

    DB-9 RS232 26-pin debug connector Debug Connector Transceiver Module DB-9 Connector Transceiver Oscillators: 32.768 KHz ColdFire® MCF5251 11.2896 MHz 24 MHz GPIO Addr Data Connectors [24:1] [31:16] Flash (-CS0) Headphone Audio DAC 16 bit,3.3v Socket (I2S2) Audio ADC SDRAM Phono plugs (I2S3) 16bit 3.3V Optical EBU...

  • Page 9: Serial Communication Channels

    The MCF5251 processor has 128 Kbytes of internal SRAM organized as 2 banks of 64 Kbytes. The SRAM can be used for either data or instruction space. There is one SDRAM (U12) device on the PCB. The system ships with 1 x 4 Mbytes x 16 of SDRAM totalling 8 Mbytes of volatile memory.
  • Page 10 dBUG> RS-232 Terminal or PC +7.0 to +14 VDC Input Power Figure 1-2 Minimum System Configuration M5251C3 Evaluation Board Users Guide, Rev. 0 Freescale Semiconductor...

  • Page 11: Installation And Setup

    Installation and Setup This section discusses all the steps needed to prepare the board for operation. Read all the sections carefully before using the board. When you are preparing the board for the first time, be sure to check that all jumpers are in the default locations.

  • Page 12: Providing Power To The Board

    1.6.3 Providing Power to the Board The board accepts three means of power supply connection—P1, P2, or J4. Connector P1 is a 2.1 mm power jack, P2 is a lever-actuated connector, and J4 is a PC disk drive-type power connector. The board accepts +7 V to +14 V DC at 1.0 amp via either of the connectors.

  • Page 13: Using A Personal Computer As A Terminal

    1.6.7 Using a Personal Computer as a Terminal A personal computer may be used as a terminal provided a terminal emulation software package is available. Examples of this software are PROCOMM, KERMIT, QMODEM, Windows 95/98/2000/XP Hyper Terminal or similar packages. The board should then be connected as described in Section 1.6.6, “Connecting the Terminal.”...
  • Page 14 Figure 1-4 Default Jumper Locations M5251C3 Evaluation Board Users Guide, Rev. 0 Freescale Semiconductor...

  • Page 15: System Power-Up And Initial Operation

    System Power-up and Initial Operation When all of the cables are connected to the board, power may be applied. The dBUG ROM Monitor initializes the board and then displays a power-up message on the terminal, which includes the amount of memory present on the board.
  • Page 16 Table 1-2 Jumper Settings (Continued) Jumper Setting Function JP10 Not fitted External 1.2V (core) supply current measurement JP11,JP13 Not fitted I2S0 5V pull-up (SDA0 and SCL0) JP12 ** Fitted External 3.3V (pad) supply current measurement JP14 ** 1-2 1.2V (core) supply from internal regulator 1.2V (core) supply from external regulator JP15 * 1-2...

  • Page 17: Using The Bdm Port

    Using the BDM Port The MCF5251 microprocessor has a built in debug module referred to as BDM (background debug module). In order to use the BDM, simply connect the 26-pin debug connector on the board (J12) to the P&E BDM wiggler cable provided in the kit. No special setting is needed. Refer to the ColdFire® User's Guide BDM section for additional instructions.
  • Page 18 M5251C3 Evaluation Board Users Guide, Rev. 0 1-12 Freescale Semiconductor...

  • Page 19: Using The Monitor/Debug Firmware

    Chapter 2 Using the Monitor/Debug Firmware The M5251C3 single board computer has a resident firmware package that provides a self-contained programming and operating environment. The firmware, named dBUG, provides the user with monitor/debug interface, in-line assembler and disassembly, program download, register and memory manipulation, and I/O control functions.

  • Page 20: Operational Procedure

    An additional function called the “TRAP 15 handler” allows the user program to utilize various routines within dBUG. The TRAP #15 handler is discussed in Section 2.5, “TRAP #15 Functions” on page 2-22. The operational mode of dBUG is shown in Figure 2-1.

  • Page 21: System Initialization

    Figure 2-1 Flow Diagram of dBUG Operational Mode 2.2.2 System Initialization The act of powering up the board will initialize the system. The processor is reset and dBUG is invoked. dBUG performs the following configurations of internal resources during the initialization. The instruction cache is invalidated and disabled.

  • Page 22: Hard Reset Button

    of the exception table is made at address $00000000 in SDRAM. To take over an exception vector, the user places the address of the exception handler in the appropriate vector in the vector table located at 0x00000000, and then points the VBR to 0x00000000. The Software Watchdog Timer is disabled and internal timers are placed in a stop condition.

  • Page 23: Command Line Usage

    Command Line Usage The user interface to dBUG is the command line. A number of features have been implemented to achieve an easy and intuitive command line interface. dBUG assumes that an 80 x 24 ASCII-character dumb terminal is used to connect to the debugger. For serial communications, dBUG requires eight data bits, no parity, and one stop bit (8N1).

  • Page 24: Asm (Assembler)

    Table 2-1 dBUG Command Summary (Continued) Mnemonic Syntax Description dc value Data Convert di<addr> Disassemble dl <offset> Download Serial dn <-c> <-e> <-i> <-s <-o offset>> <filename> Download Network go <addr> Execute gt addr Execute To HELP help <command> Help ird <module.register>...

  • Page 25: Bc (Block Compare)

    For the interactive mode, the user enters the command and the optional <addr>. If the address is not specified, then the last address is used. The memory contents at the address are disassembled, and the user prompted for the new assembly. If valid, the new assembly is placed into memory, and the address incremented accordingly.

  • Page 26: Bm (Block Move)

    The optional value <inc> can be used to increment (or decrement) the data value during the fill. This command first aligns the starting address for the data access size, and then increments the address accordingly during the operation. Thus, for the duration of the operation, this command performs properly-aligned memory accesses.

  • Page 27: Br (Breakpoints)

    2.4.5 BR (Breakpoints) Usage: BR addr <-r> <-c count> <-t trigger> The BR command inserts or removes breakpoints at address addr. The value for addr may be an absolute address specified as a hexadecimal value, or a symbol name. Count and trigger are numbers converted according to the user-defined radix, normally hexadecimal.

  • Page 28: Dc (Data Conversion)

    This command first aligns the starting address for the data access size, and then increments the address accordingly during the operation. Thus, for the duration of the operation, this command performs properly-aligned memory accesses. Examples: To search for the 16-bit value 0x1234 in the memory block starting at 0x00040000 and ending at 0x00080000: bs 40000 80000 1234 This reads the 16-bit word located at 0x00040000 and compares it against the 16-bit value 0x1234.

  • Page 29: Dl (Download Console)

    Wherever possible, the disassembler will use information from the symbol table to produce a more meaningful disassembly. This is especially useful for branch target addresses and subroutine calls. The DI command attempts to track the address of the last disassembled opcode. If no address is provided to the DI command, then the DI command uses the address of the last opcode that was disassembled.

  • Page 30: Go (Execute)

    in conjunction with the -s option to indicate an optional offset for S-record download. The filename is passed directly to the TFTP server and therefore must be a valid filename on the server. If neither of the -c, -e, -i, -s or filename options are specified, then a default filename and filetype will be used.

  • Page 31: Gt (Execute To)

    To execute code at the C function main(), the command is: go _main To execute code at the address 0x00040000, the command is: go 40000 2.4.12 GT (Execute To) Usage: GT addr The GT command inserts a temporary breakpoint at addr and then executes target code starting at the current program counter.

  • Page 32: Help (Help)

    UART0, and UART1. Refer to the MCF5407 Reference Manual for more information on these modules and the registers they contain. Example: To modify the TMR register of the first Timer module to the value 0x0021, the command is: irm timer1.tmr 0021 2.4.15 HELP (Help) Usage: HELP <command>...

  • Page 33: Md (Memory Display)

    2.4.18 MD (Memory Display) Usage: MD <width> <begin> <end> The MD command displays a contiguous block of memory starting at address begin and stopping at address end. The values for addresses begin and end may be absolute addresses specified as hexadecimal values, or symbol names.

  • Page 34: Mmap (Memory Map Display)

    Examples: To set the byte at location 0x00010000 to be 0xFF, the command is: mm.b 10000 FF To interactively modify memory beginning at 0x00010000, the command is: mm 10000 2.4.20 MMAP (Memory Map Display) Usage: mmap This command displays the memory map information for the M5251C3 evaluation board. The information displayed includes the type of memory, the start and end address of the memory, and the port size of the memory.

  • Page 35: Rm (Register Modify)

    Here is an example of the output from this command: PC: 00000000 SR: 2000 [t.Sm.000...xnzvc] An: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 01000000 Dn: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 2.4.22 RM (Register Modify) Usage: RM reg data The RM command modifies the contents of the register reg to data.

  • Page 36: Show (Show Configurations)

    • client—This is the network Internet Protocol (IP) address of the board. For network communications, the client IP is required to be set to a unique value, usually assigned by your local network administrator. • server—This is the network IP address of the machine which contains files accessible via TFTP. Your local network administrator will have this information and can assist in properly configuring a TFTP server if one does not exist.

  • Page 37: Step (Step Over)

    client: 192.0.0.2 gateway: 0.0.0.0 netmask: 255.255.255.0 filename: test.srec filetype: S-Record mac: 00:CF:52:49:C3:01 2.4.26 STEP (Step Over) Usage: STEP The STEP command can be used to “step over” a subroutine call, rather than tracing every instruction in the subroutine. The ST command sets a temporary breakpoint one instruction beyond the current program counter and then executes the target code.

  • Page 38: Trace (Trace Into)

    To remove the symbol “junk” from the table, the command is: symbol -r junk To see how full the symbol table is, the command is: symbol -s To display the symbol table, the command is: symbol -l 2.4.28 TRACE (Trace Into) Usage: TRACE <num>...

  • Page 39: Version (Display Dbug Version)

    To program all 7 sectors of user Flash, the command is: upuser To program only 1000 bytes into user Flash, the command is: upuser 1000 2.4.31 VERSION (Display dBUG Version) Usage: VERSION The VERSION command displays the version information for dBUG. The dBUG version, build number and build date are all given.

  • Page 40: Trap #15 Functions

    TRAP #15 Functions An additional utility within the dBUG firmware is a function called the TRAP 15 handler. This function can be called by the user program to utilize various routines within the dBUG, to perform a special task, and to return control to the dBUG. This section describes the TRAP 15 handler and how it is used. There are four TRAP #15 functions.

  • Page 41: Char_Present

    asm (“ trap#15”); /* make the call */ asm (“ move.ld1,d0”); /* put the character in d0 */ 2.5.3 CHAR_PRESENT This function (function code 0x0014) checks if an input character is present to receive. A value of zero is returned in D0 when no character is present. A non-zero value in D0 means a character is present. Assembly example: move.l #$0014,d0...
  • Page 42 M5251C3 Evaluation Board Users Guide, Rev. 0 2-24 Freescale Semiconductor...

  • Page 43: Hardware Description And Reconfiguration

    Chapter 3 Hardware Description and Reconfiguration This chapter provides a functional description of the M5251C3 board hardware. With the description given here and the schematic diagrams in Appendix A, the user can gain a good understanding of the board's design. In this manual, an active low signal is indicated by a "-" preceding the signal name in the text and a bar over the signal name in the schematics.

  • Page 44: Hiz Signal

    points to the Flash memory. The contents of the exception table are written to address $00000000 in the SDRAM. The Software Watchdog Timer is disabled, the Bus Monitor is enabled, and the internal timers are placed in a stop condition. The interrupt controller registers are initialized with unique interrupt level/priority pairs.

  • Page 45: Internal Sram

    • Software watchdog timer module • Two general purpose timer modules • UART module • C module • Audio interface modules • DMA module • QSPI module • CAN module • USB module • ATA module • Flash media module All external interrupt inputs are edge sensitive.

  • Page 46: Reset Vector Mapping

    -TA generation for each chip-select. These registers are programmed by the dBUG monitor to map the external memory and I/O devices. The M5251C3 uses the following signals to select external peripherals: -CS0 to enable the Flash ROM (See Section 3.1.13, “Flash ROM.”) -SDRAS, -SDCAS, and -SDRAM_CS1 to enable the SDRAM (See Section 3.1.12,...

  • Page 47: Ta Generation

    3.1.10 TA Generation The processor starts a bus cycle by asserting -CSx with the other control signals. The processor then waits for a transfer acknowledgment (-TA) either from within (Auto acknowledge - AA mode) or from the externally addressed device before it can complete the bus cycle. -TA is used to indicate the completion of the bus cycle.

  • Page 48: Qspi Module

    3.2.2 QSPI Module The QSPI (Queued Serial Peripheral Interface) module provides a serial peripheral interface with queued transfer capability. It will support up to 16 stacked transfers at one time, minimizing CPU intervention between transfers. Transfer RAMs in the QSPI are indirectly accessible using address and data registers. Functionality is very similar, but not identical, to the QSPI portion of the QSM (Queued Serial Module) implemented in the MC68332 processor.

  • Page 49: Usb 2.0 Otg Module

    — 0–8 bytes data length — Programmable bit rate up to 1 Mbps — Content-related addressing • Up to 32 flexible message buffers of zero to eight bytes data length, each configurable as Rx or Tx, all supporting standard and extended messages •...

  • Page 50: General Purpose I/O Pins

    General Purpose I/O Pins The MCF5251 offers 60-bits of general-purpose I/O of which 6 are dedicated general purpose inputs and 3 are dedicated general purpose outputs. Seven of the GPIO lines are also available as edge sensitive interrupt inputs plus one dedicated pin is used to generate a WAKEUP interrupt from low power mode. The functions of all I/O pins are individually programmable, since they are multiplexed with other pin functions.

  • Page 51: Flash Memory Card/Ide Interface Module

    Flash Memory Card/IDE Interface Module The SCF5251 memory bus allows connection of an IDE hard disk drive or SmartMedia flash card with a minimum of external hardware. It can interface with both an IDE device and a SmartMedia device connected, although both cannot be supported simultaneously, as the IDE-DIOR and IDE-DIOW signals can only be used to interface to one or the other.
  • Page 52 -BKPT DEVELOPER RESERVED DSCLK DEVELOPER RESERVED -RESET I/O or Pad Voltage PST3 PST2 PST1 PST0 DDATA3 DDATA2 DDATA1 DDATA0 FREESCALE RESERVED FREESCALE RESERVED PSTCLK Core Voltage Figure 3-1 J12 Connector Pin Assignment M5251C3 Evaluation Board Users Guide, Rev. 0 3-10 Freescale Semiconductor...

  • Page 53: Appendix A Schematics

    Appendix A Schematics This section is composed of the schematics for the M5251C3 Evaluation Board, including the schematic for the MCF5251 Evaluation Board. M5251C3 Evaluation Board Users Guide, Rev. 0 Freescale Semiconductor...
  • Page 54 Figure 3-2 shows the Hierarchical Block Diagram. Debug andTest Points PST0/GPIO50 PST1/GPIO49 PST2/INTMON2/GPIO48 PST3/INTMON1/GPIO47 WAKEUP/GPIO21 PSTCLK/GPIO51 -RESET DDATA0/CTS1_B/SDATA0_SDIO1/GPIO1 DDATA0/CTS1_B/SDATA0_SDIO1/GPIO1 DDATA1/RTS1_B/SDATA2_BS2/GPIO2 Sheet2 DDATA2/CTS0_B/GPIO3 DDATA3/RTS0_B/GPIO4 Audio SDATAI3/GPIO8 DSCLK SCLK3/GPIO35 -BKPT LRCK3/GPIO43 SDATAO2/GPIO34 SCLK2/GPIO22 -CS0/CS4 LRCK2/GPIO23 EBUIN1/GPIO36 BCLK EBUOUT1/GPIO37 -RESET MCLK1/GPIO11 -TA/GPIO12 MCLK2/QSPI_CS2/GPIO24 WAKEUP/GPIO21 WAKEUP/GPIO21 LINOUT...
  • Page 55 Figure 3-3 shows the Audio Interface. BEAD (100MHz) Analog right channel input 4x 4.7K Analog ground AINR RCA PHONO JACK AINL VREF 4.7uF 25V 470R MCLK1/GPIO11 VCOM SCLK3/GPIO35 AGND SCLK MCLK MCLK2/QSPI_CS2/GPIO24 LRCK LRCK3/GPIO43 DGND SDTO SDATAI3/GPIO8 Analog left channel input AK5353VT RCA PHONO JACK 2.2nF...
  • Page 56 Figure 3-4 shows the separate schematic for the MCF5251 Evaluation Board. +3.3VP JP14 selects between core running +1.2VP +3.3VP from internal or external 1.2V supply C115 C101 C130 C103 C131 C100 C129 C106 C108 C104 C105 C107 C102 Default setting - connect pins 1+2. VRTC 0.1uF 0.1uF...
  • Page 57 Figure 3-5 shows the Debug and Test Points. +3.3V Shrouded BDM Header IMPORTANT NOTE: ONLY a 3.3V BDM debugging cable can be used with the -BKPT DSCLK MCF5250 processor. -RESET PST3/INTMON1/GPIO47 PST2/INTMON2/GPIO48 PST1/GPIO49 JP21 PST0/GPIO50 DDATA3/RTS0_B/GPIO4 JP23 JP27 DDATA2/CTS0_B/GPIO3 DDATA1/RTS1_B/SDATA2_BS2/GPIO2 JP28 DDATA0/CTS1_B/SDATA0_SDIO1/GPIO1 PSTCLK/GPIO51...
  • Page 58 Figure 3-6 shows the IDE, ATA, and Wireless. A[16:1] Uni-directional A[23:1] BUFA1 BUFA2 BUFA3 BUFA4 BUFA5 BUFA6 BUFA7 BUFA8 BUFA9 BUFA10 BA11 BA12 BA13 BA16 BA14 +3.3V BA15 +3.3V RP36 1DIR VCC-1 VCC-2 +3.3V VCC-3 +3.3V 2DIR VCC-4 RP28 4x 4.7K 4x 10K GND-1 GND-5...
  • Page 59 Figure 3-7 shows Memory. +3.3V BEAD (100MHz) A[23:1] D[31:16] D[31:16] D[31:16] Flash memory SDRAM memory 4.7K NC#36 BYTE# NC#40 VSS-1 DQ15/A-1 VDD-1 VDD-2 DQ14 VDD-3 DQ13 VDDQ-1 NC-1 DQ12 VDDQ-2 VDDQ-3 -RESET RESET# VCC-2 DQ10 VDDQ-4 NC-2 DQ11 DQ11 NC-3 DQ12 VSSQ-1 RY/BY#...
  • Page 60 Figure 3-8 shows Power Supply. DC voltage input range +7 to +14V Switchcraft RAPC712 must be +12V for XTRIM operation Power Jack Connector - 2.1mm diameter NOTE: the positive terminal of each power connector is shown on the silkscreen of 3.3V Regulator +3.3V the PCB...
  • Page 61 Figure 3-9 shows Serial Interfaces and Clocks. +3.3V 24 MHz 11.2896 MHz NOTE: The I2C/Mbus on the MCF5251 will USBCRIN USBCROUT CRIN CROUT support both 3.3V & 5V devices. QSPI_CLK QSPI_DIN QSPI_DOUT EBUIN4/QSPI_CS0/GPIO15 RP29 EBUOUT2/QSPI_CS1/GPIO16 JP19 MCLK2/QSPI_CS2/GPIO24 JP16 -CS1/QSPI_CS3/GPIO28 22pF 22pF 22pF 22pF...
  • Page 62 Figure 3-10 shows Trio Peripherals. +3.3V POT1 LCD1 LK11 ADIN4/GPI56 BAS70-05 +3.3V LK10 PLAY / PAUSE / MENU-UP +3.3V 100K VOUT ADIN0/GPI52 Sony I/F Philips I/F +3.3V CD_DATA SDATAI SDATAI1/GPIO17 QSPI_DOUT MENU SELECT CD_BCK SCLK SCLK1/GPIO20 QSPI_CLK CD_LRCK LRCK LK13 EBUIN4/QSPI_CS0/GPIO15 LRCK1/GPIO19 CD-SCLK...

  • Page 63: Appendix B Evaluation Board Bom

    Appendix B Evaluation Board BOM Table B-1 lists the bill of materials. Table B-1 M5251C3 BOM Item Reference Part Function ANT1 392-8093 2.45GHz_WLAN_Antenna BA11 BA12 BA13 BA14 BA15 BA16 BT ENA ENB FLGA FLGB OUTB SPARE WLAN 524-864 3.6V NiMH/15mAh C1 C19 C20 C22 C30 C73 C74 C75 C76 C83 Cap, 1nF,NPO or COG, 25v, C84 C85 C95 C101 C111 C113 C115 C135...
  • Page 64 Table B-1 M5251C3 BOM (Continued) Item Reference Part Function C117 C123 C1608C0G1H222J Cap, 2.2nF,NPO or COG, 25v, 0603,5% D5 D9 D10 D27 D28 AA3528EC LED, 1206, SMT. Red D6 D7 D8 MBRS340T3 D11 D12 D22 AA3528SGC LED, 1206, SMT. Green D23 D25 BB132 BAT754S...
  • Page 65 Table B-1 M5251C3 BOM (Continued) Item Reference Part Function L1 L2 B82111-B-C24 L3 L4 L7 L8 L9 L10 L11 L12 L13 BLM21A601S 1210-331K 0.3uH or 0.33uh, 1210 LCD1(socket) M22-6112022 or Socket for LCD1, LDC1 is MMS-120-01-L-SV PSG7955AW-SGR-3 LCD2(socket 9-188275-0 Socket for LCD2, LCD2 is MOBI3007 LK1 LK2 LK3 LK4 LK5 LK6 LK7 LK8 LK9 LINK...
  • Page 66 Table B-1 M5251C3 BOM (Continued) Item Reference Part Function R97 R102 R104 R105 R144 270R R98 R123 R126 R152 R155 R106 560R R107 R108 R140 470R R119 R120 R129 R130 R139 R147 R132 R138 270K R142 R150 R148 R149 R153 R154 120R R156 R157...
  • Page 67 Table B-1 M5251C3 BOM (Continued) Item Reference Part Function MAX3225CAP IC, 16 PIN TSSOP M25P40-VMN6T IC SRL FLASH 4MBIT 3.6V 8-SOIC U16 U17 MC74LCX16245DT IC, 48 PIN, TSSOP,3.3V, 16 BIT TRANSCEIVER TLC7733ID IC, 8 PIN, SOIC AK5353VT IC, 16 PIN,TSSOP GP1FA550RZ GP1FA550RZ REPLACEMENT REPLACEMENT PART...
  • Page 68 M5251C3 Evaluation Board Users Guide, Rev. 0 Freescale Semiconductor...

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