NXP Semiconductors MPC555 User Manual

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Freescale Semiconductor, Inc.

MPC555 / MPC556

USER'S MANUAL

Revised 15 October 2000

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For More Information On This Product,

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Page 1 Freescale Semiconductor, Inc. MPC555 / MPC556 USER’S MANUAL Revised 15 October 2000  Copyright 2000 MOTOROLA; All Rights Reserved For More Information On This Product, Go to: www.freescale.com...
Page 2 Freescale Semiconductor, Inc. MPC555 / MPC556 USER’S MANUAL Revised 15 October 2000  Copyright 2000 MOTOROLA; All Rights Reserved For More Information On This Product, Go to: www.freescale.com...
Page 3: Table Of Contents
1.3 MPC555 / MPC556 Address Map ........
Page 4 2.3.3.5 VF[0:2]/MPIO32B[0:2] ..........2-23 MPC555 / MPC555...
Page 5 2.4.6.2 Encoded 3-V / 5-V Select ..........2-31 MPC555 / MPC555...
Page 6 3.2 RCPU Block Diagram............3-2 MPC555 / MPC555...
Page 7 3.11.4 Precise Exceptions ........... . 3-35 MPC555 / MPC555...
Page 8 3.15.4.1 System Reset Interrupt..........3-44 MPC555 / MPC555...
Page 9 4.5.1 Exception Table Relocation Operation ........4-17 MPC555 / MPC555...
Page 10 6.6 MPC555 / MPC556 Decrementer ........
Page 11 8.2 System Clock Sources ............8-3 MPC555 / MPC555...
Page 12 8.6 MPC555 / MPC556 Internal Clock Signals ........
Page 13 9.5.13 Show Cycle Transactions ..........9-54 MPC555 / MPC555...
Page 14 11.6.1 The Reservation Protocol ..........11-7 MPC555 / MPC555...
Page 15 13.3.3 External Trigger Input Pins ..........13-4 MPC555 / MPC555...
Page 16 13.12.5 Port Data Direction Register ......... . . 13-35 MPC555 / MPC555...
Page 17 14.7.5 Master Mode Operation ..........14-33 MPC555 / MPC555...
Page 18 14.9.11 QSCI1 Receive Queue Software Flow Chart ......14-72 MPC555 / MPC555...
Page 19 15.12.1.1 MPWMSM Period Register (MPWMSMPERR) ......15-27 15.12.1.2 MPWMSM Pulse Width Register (MPWMSMPULR) ....15-27 MPC555 / MPC555 TABLE OF CONTENTS MOTOROLA USER’S MANUAL...
Page 20 16.4.1 TouCAN Reset ............16-11 MPC555 / MPC555...
Page 21 17.3.1 Event Timing............17-3 MPC555 / MPC555...
Page 22 18.4.3 Reset Operation ............18-7 MPC555 / MPC555...
Page 23 19.1.1 MPC555 / MPC556 CMF Features........
Page 24 21.3.1.4 Context Dependent Filter ......... . 21-15 MPC555 / MPC555...
Page 25 21.7.4 Breakpoint Address Register (BAR) ........21-46 21.7.5 Comparator G–H Value Registers (CMPG–CMPH) ......21-46 MPC555 / MPC555 TABLE OF CONTENTS MOTOROLA USER’S MANUAL...
Page 26 22.9 Boundary Scan Register ........... . 22-7 Appendix A MPC555 / MPC556 INTERNAL MEMORY MAP Appendix B...
Page 27 E.2 MPC555 / MPC556 Family Power Distribution ........
Page 28 H.2 Programming and Erase Algorithm ..........H-3 INDEX Online publishing by JABIS, http://www.jabis.com MPC555 / MPC555 TABLE OF CONTENTS MOTOROLA USER’S MANUAL...
Page 29 MPC555 / MPC556 Block Diagram ..............1-2 MPC555 / MPC556 Memory Map ..............1-6 MPC555 / MPC556 Internal Memory Map ............1-7 MPC555 / MPC556 Case Dimensions and Packaging ........2-2 MPC555 / MPC556 Pinout Data ..............2-3 Type A Interface ................... 2-39 Type B Interface ...................
Page 30 Divided System Clocks Timing Diagram ............8-11 Clocks Timing For DFNH = 1 (or DFNL = 0) ..........8-12 Clock Source Flow Chart ................8-14 MPC555 / MPC556 Low-Power Modes Flow Diagram ......... 8-19 8-10 Basic Power Supply Configuration ............... 8-22 8-11 External Power Supply Scheme ..............
Page 31 Basic Flow of an External Master Write Access ........... 9-49 9-36 Peripheral Mode: External Master Reads from MPC555 / MPC556 — Two Wait States ........... 9-50 9-37 Peripheral Mode: External Master Writes to MPC555 / MPC556; Two Wait States ..................9-51 9-38 Flow of Retry of External Master Read Access ..........
Page 32 Memory Controller Function Within the USIU ..........10-1 10-2 Memory Controller Block Diagram ..............10-2 10-3 MPC555 / MPC556 Simple System Configuration ........10-3 10-4 Bank Base Address and Match Structure ............. 10-4 10-5 MPC555 / MPC556 GPCM–Memory Devices Interface ....... 10-7...
Page 33 15-12 MIOS1 Example: Pulse Width Modulation Output ........15-43 16-1 TouCAN Block Diagram ................16-1 16-2 Typical CAN Network ................... 16-3 MPC555 / MPC555 LIST OF FIGURES MOTOROLA USER’S MANUAL Rev. 15 October 2000 xxxiii For More Information On This Product,...
Page 34 21-3 Instruction Support General Structure ............21-17 21-4 Load/Store Support General Structure ............21-20 21-5 Functional Diagram of MPC555 / MPC556 Debug Mode Support ..... 21-23 21-6 Debug Mode Logic ..................21-25 21-7 Debug Mode Reset Configuration .............. 21-27 21-8 Asynchronous Clock Serial Communications ..........
Page 35 SIOP Function Data Transition Example ............D-53 MPC555 / MPC556 Family Power Distribution Diagram — 3 V ..... E-2 MPC555 / MPC556 Family Power Distribution Diagram — 5 V and Analog .. E-3 Crystal Oscillator Circuit ................. E-4 RC Filter Example ..................E-5 Bypass Capacitors Example (Alternative) ............
Page 36 Rising Edge Timing Diagram ............... G-61 G-38 MPWMSM Interrupt Flag to MPWMO Output Pin Falling Edge Timing Diagram ................... G-62 G-39 MMCSM Minimum Input Pin (Either Load or Clock) MPC555 / MPC555 LIST OF FIGURES MOTOROLA USER’S MANUAL Rev. 15 October 2000 xxxvi For More Information On This Product, Go to: www.freescale.com...
Page 37 G-50 MPIOSM Input Pin to MPIOSM_DR (Data Register) Timing Diagram ................... G-68 Typical Program Time vs. V and Temperature (for CDR1 “Target” Process) ................H-2 MPC555 / MPC555 LIST OF FIGURES MOTOROLA USER’S MANUAL Rev. 15 October 2000 xxxvii For More Information On This Product,...
Page 38 Freescale Semiconductor, Inc. Figure Page Number Number MPC555 / MPC555 LIST OF FIGURES MOTOROLA USER’S MANUAL Rev. 15 October 2000 xxxviii For More Information On This Product, Go to: www.freescale.com...
Page 39 Table Page Number Number 2-1 MPC555 / MPC556 Pin Functions for 272-Pin PBGA ........... 2-4 2-2 Pin Functionality Table ..................2-7 2-3 PDMCR Bit Descriptions..................2-29 2-4 Pin Reset State....................2-32 2-5 Pad Groups Based on 3-V / 5-V Select ............... 2-57 2-6 Pin Names and Abbreviations ................
Page 40 8-9 SCCR Bit Descriptions..................8-30 8-10 PLPRCR Bit Descriptions ................. 8-34 8-11 COLIR Bit Descriptions..................8-36 8-12 VSRMCR Bit Descriptions ................8-36 9-1 MPC555 / MPC556 SIU Signals ................9-4 9-2 Data Bus Requirements For Read Cycles............9-30 MPC555 / MPC556 LIST OF TABLES MOTOROLA USER’S MANUAL...
Page 41 13-4 QADC64 Clock Programmability ..............13-28 13-5 QADC64 Status Flags and Interrupt Sources..........13-30 13-6 QADC64 Address Map ..................13-32 13-7 QADC64MCR Bit Descriptions ............... 13-33 13-8 QADC64INT Bit Descriptions................13-34 MPC555 / MPC556 LIST OF TABLES MOTOROLA USER’S MANUAL Rev. 15 October 2000 For More Information On This Product, Go to: www.freescale.com...
Page 42 14-28 Serial Frame Formats ..................14-51 14-29 Examples of SCIx Baud Rates ..............14-52 14-30 QSCI1CR Bit Descriptions................14-60 14-31 QSCI1SR Bit Descriptions ................14-61 15-1 MIOS1 I/O Ports ....................15-8 MPC555 / MPC556 LIST OF TABLES MOTOROLA USER’S MANUAL Rev. 15 October 2000...
Page 43 16-6 Receive Mask Register Bit Values..............16-8 16-7 Mask Examples for Normal/Extended Messages ..........16-8 16-8 Example IMB Clock, CAN Bit Rate and S-Clock Frequencies......16-9 16-9 Interrupt Levels ....................16-19 MPC555 / MPC556 LIST OF TABLES MOTOROLA USER’S MANUAL Rev.
Page 44 18-1 DPTRAM Register Map ..................18-3 18-2 DPTMCR Bit Descriptions ................18-4 18-3 RAMBAR Bit Descriptions ................18-5 19-1 CMF Register Programmer’s Model ..............19-5 19-2 CMFMCR Bit Descriptions................. 19-6 MPC555 / MPC556 LIST OF TABLES MOTOROLA USER’S MANUAL Rev. 15 October 2000...
Page 45 21-25 Breakpoint Counter A Value and Control Register (COUNTA)...... 21-52 21-26 Breakpoint Counter B Value and Control Register (COUNTB)..... 21-53 21-27 ECR Bit Descriptions ..................21-54 21-28 DER Bit Descriptions ..................21-55 MPC555 / MPC556 LIST OF TABLES MOTOROLA USER’S MANUAL Rev.
Page 46 G-12 Interrupt Timing....................G-39 G-13 Debug Port timing .................... G-40 G-14 RESET Timing ....................G-43 G-15 JTAG Timing ....................G-47 G-16 QADC64 Conversion Characteristics (Operating) ........... G-52 MPC555 / MPC556 LIST OF TABLES MOTOROLA USER’S MANUAL Rev. 15 October 2000...
Page 47 H-1 Program and Erase Characteristics ..............H-1 H-2 CMF AC and DC Power Supply Characteristics ...........H-2 H-3 Flash Module Life....................H-3 H-4 CMF Programming Algorithm (v5) ................H-3 H-5 CMF Erase Algorithm (v5)..................H-3 MPC555 / MPC556 LIST OF TABLES MOTOROLA USER’S MANUAL Rev. 15 October 2000...
Page 48 Freescale Semiconductor, Inc. Page Table Number Number MPC555 / MPC556 LIST OF TABLES MOTOROLA USER’S MANUAL Rev. 15 October 2000 xlviii For More Information On This Product, Go to: www.freescale.com...
Page 49 Freescale Semiconductor, Inc. PREFACE This manual defines the functionality of the MPC555 / MPC556 for use by software and hardware developers. The MPC555 / MPC556 is based on the PowerPC proces- sor used in the Motorola MPC500 family of microcontrollers. For further information...
Page 50 LSB means least significant bit or bits. MSB means most significant bit or bits. Ref- erences to low and high bytes are spelled out. MPC555 / MPC556 PREFACE MOTOROLA USER’S MANUAL Rev.
Page 51: Block Diagram
Freescale Semiconductor, Inc. SECTION 1 OVERVIEW The MPC555 / MPC556 is a member of Motorola’s MPC500 PowerPC RISC Micro- controller family. The MPC555 / MPC556 offers the following features: • PowerPC core with floating-point unit • 26 Kbytes fast RAM and 6 Kbytes TPU microcode RAM •...
Page 52: Mpc555 / Mpc556 Features
Figure 1-1 MPC555 / MPC556 Block Diagram 1.2 MPC555 / MPC556 Features Features of each module on the MPC555 / MPC556 are listed below. 1.2.1 RISC MCU Central Processing Unit (RCPU) • 32-bit PowerPC architecture (compliant with PowerPC Architecture Book 1) •...
Page 53: Four-Bank Memory Controller
• External 4.75-V to 5.25-V program and erase power supply 1.2.6 26 Kbytes of Static RAM • One 16-Kbyte and one 10-Kbyte module • Fast (one-clock) access • Keep-alive power • Soft defect detection (SDD) MPC555 MPC556 OVERVIEW MOTOROLA USER’S MANUAL Rev. 15 October 2000 For More Information On This Product, Go to: www.freescale.com...
Page 54: General-Purpose I/O Support
• Two conversion command queues of variable length • Automated queue modes initiated by: — External edge trigger/level gate — Software command • 64 result registers • Output data that is right- or left-justified, signed or unsigned MPC555 MPC556 OVERVIEW MOTOROLA USER’S MANUAL Rev. 15 October 2000 For More Information On This Product, Go to: www.freescale.com...
Page 55: Two Can 2.0B Controller Modules (Toucans)
— Multiplexing of transmit data pins with discrete outputs and receive data pins with discrete inputs 1.3 MPC555 / MPC556 Address Map The internal memory map is organized as a single 4-Mbyte block. The user can assign this block to one of eight locations by programming a register in the USIU. The eight...
Page 56: Mpc555 / Mpc556 Memory Map
0x01BF FFFF 0x01C0 0000 0x01FF FFFF 0xFFFF FFFF Figure 1-2 MPC555 / MPC556 Memory Map The internal memory space is divided into the following sections: • Flash memory (448 Kbytes) • Static RAM memory (26 Kbytes) • Control registers and IMB2 modules (64 Kbytes): —...
Page 57: Mpc555 / Mpc556 Internal Memory Map
0x 3F C000 SRAM B UIMB_Registers 0x 3F (16 Kbytes) FFFF (128 bytes) 0x30 7FFF Figure 1-3 MPC555 / MPC556 Internal Memory Map MPC555 MPC556 OVERVIEW MOTOROLA USER’S MANUAL Rev. 15 October 2000 For More Information On This Product, Go to: www.freescale.com...
Page 58 Freescale Semiconductor, Inc. MPC555 MPC556 OVERVIEW MOTOROLA USER’S MANUAL Rev. 15 October 2000 For More Information On This Product, Go to: www.freescale.com...
Page 59: Signal Descriptions
Freescale Semiconductor, Inc. SECTION 2 SIGNAL DESCRIPTIONS 2.1 Packaging and Pinout Descriptions Figure 2-1 gives the case configuration and packaging information for the MPC555 / MPC556. Figure 2-2 gives the MPC555 / MPC556 pinout data. Table 2-1 gives an overview of the pins on the MPC555 / MPC556.
Page 60: Mpc555 / Mpc556 Case Dimensions And Packaging
6 7 8 9 10 11 12 13 14 15 16 17 18 19 272X BOTTOM VIEW 0.15 CASE 1135A–01 ISSUE B Figure 2-1 MPC555 / MPC556 Case Dimensions and Packaging MPC555 MPC556 SIGNAL DESCRIPTIONS MOTOROLA USER’S MANUAL Rev. 15 October 2000 For More Information On This Product, Go to: www.freescale.com...
Page 61: Mpc555 / Mpc556 Pinout Data
Freescale Semiconductor, Inc. Figure 2-2 MPC555 / MPC556 Pinout Data MPC555 MPC556 SIGNAL DESCRIPTIONS MOTOROLA USER’S MANUAL Rev. 15 October 2000 For More Information On This Product, Go to: www.freescale.com...
Page 62 Freescale Semiconductor, Inc. Table 2-1 MPC555 / MPC556 Pin Functions for 272-Pin PBGA Functional Group Signals Pins 3 V / 5 V 24 Address lines ADDR[8:31]/SGPIOA[8:31] (16-Mbyte address space) 3-V / 5-V GPIO 32-bit data bus DATA[0:31]/SGPIOD[0:31] IRQ[0]/SGPIOC[0] IRQ[1]/RSV/SGPIOC[1] IRQ[2]/CR/SGPIOC[2]/MTS...
Page 63 Freescale Semiconductor, Inc. Table 2-1 MPC555 / MPC556 Pin Functions for 272-Pin PBGA (Continued) Functional Group Signals Pins 3 V / 5 V XTAL EXTAL CLKOUT Clocks and PLL EXTCLK ENGCLK/BUCLK PCS0/ SS/QGPIO[0] PCS[1:3]/QGPIO[1:3] MISO/QGPIO[4] MOSI/QGPIO[5] QSMCM SCK/QGPIO[6] TXD[1:2]/QGPO[1:2] RXD[1:2]/QGPI[1:2]...
Page 64: Pin Functionality
Freescale Semiconductor, Inc. Table 2-1 MPC555 / MPC556 Pin Functions for 272-Pin PBGA (Continued) Functional Group Signals Pins 3 V / 5 V High voltage Supply VDDH, VDDA, VRH Programming Voltage 3-V / 5-V NOTES: 1. “/” implies that the corresponding functions are multiplexed on the pin 2.
Page 65 TSIZ[0:1] — — 25 / 50 RD/WR RD/WR — — 25 / 50 BURST BURST — — 25 / 50 MPC555 MPC556 SIGNAL DESCRIPTIONS MOTOROLA USER’S MANUAL Rev. 15 October 2000 For More Information On This Product, Go to: www.freescale.com...
Page 66 VFLS[0:1] — — 25 / 50 — — — — — — — — TDI/DSDI DSDI — — — — MPC555 MPC556 SIGNAL DESCRIPTIONS MOTOROLA USER’S MANUAL Rev. 15 October 2000 For More Information On This Product, Go to: www.freescale.com...
Page 67 — — — MIOS Hysteresis, MDA[11:15] MDA[11:15] 200 / fast — Synch Hysteresis, MDA[27:31] MDA[27:31] 200 / fast — Synch MPC555 MPC556 SIGNAL DESCRIPTIONS MOTOROLA USER’S MANUAL Rev. 15 October 2000 For More Information On This Product, Go to: www.freescale.com...
Page 68 — Synch AN[52:54] — Analog — — AN[52:54]/ MA[0:2] — — — MA[0:2]/ Hysteresis, PQA[0:2] PQA[0:2] — — Synch MPC555 MPC556 SIGNAL DESCRIPTIONS MOTOROLA USER’S MANUAL Rev. 15 October 2000 2-10 For More Information On This Product, Go to: www.freescale.com...
Page 69 — Synch / No A_CNRX0 CNRX0_A — — — Synch Synch / No B_CNRX0 CNRX0_B — — — Synch MPC555 MPC556 SIGNAL DESCRIPTIONS MOTOROLA USER’S MANUAL Rev. 15 October 2000 2-11 For More Information On This Product, Go to: www.freescale.com...
Page 70: Signal Descriptions
Address Bus – Specifies the physical address of the bus transaction. The address is driven onto the bus and kept valid until a transfer acknowledge is received from the slave. ADDR8 is the most significant signal for this bus. MPC555 MPC556 SIGNAL DESCRIPTIONS MOTOROLA USER’S MANUAL...
Page 71: Data[0:31]/Sgpiod[0:31]
SGPIO – This function allows the pins to be used as general purpose inputs/outputs. Memory Transfer Start – This pin is the transfer start signal from the MPC555 / MPC556 memory controller to allow external memory access by an external bus mas- ter.
Page 72: Irq[4]/At[2]/Sgpioc[4]
RCPU. Mode Clock [2:3] – Sampled at the negation of PORESET in order to configure the PLL/clock mode of operation. 2.3.1.10 TSIZ[0:1] Pin Name: tsiz0 - tsiz1 (2 pins) MPC555 MPC556 SIGNAL DESCRIPTIONS MOTOROLA USER’S MANUAL Rev.
Page 73: Rd/Wr
This pin is an active negate signal and may need an external pull-up resistor to ensure proper operation and signal timing specifications. 2.3.1.16 TEA Pin Name: tea_b MPC555 MPC556 SIGNAL DESCRIPTIONS MOTOROLA USER’S MANUAL Rev.
Page 74: Rstconf/Texp
TEA quickly, before a second error is de- tected. That is, the pin must be pulled up within one clock cycle of the time it was three- stated by the MPC555 / MPC556. 2.3.1.17 RSTCONF/TEXP Pin Name: rstconf_b_texp Reset Configuration –...
Page 75: We[0:3]/Be[0:3]/At[0:3]
16-cycle period is taken before testing the presence of an external soft reset. To meet external timing requirements, an external pull-up device is required to negate SRESET. See SECTION 7 RESET for more details on timing. 2.3.1.25 SGPIOC[6]/FRZ/PTR Pin Name: sgpioc6_frz_ptr_b MPC555 MPC556 SIGNAL DESCRIPTIONS MOTOROLA USER’S MANUAL Rev. 15 October 2000 2-17 For More Information On This Product, Go to: www.freescale.com...
Page 76: Sgpioc[7]/Irqout/Lwp[0]
Instruction Watchpoint 2 – This output line reports the detection of an instruction watchpoint in the program flow executed by the RCPU. 2.3.1.29 BB/VF[2]/IWP[3] Pin Name: bb_b_vf2_iwp3 MPC555 MPC556 SIGNAL DESCRIPTIONS MOTOROLA USER’S MANUAL Rev. 15 October 2000...
Page 77: Iwp[0:1]/Vfls[0:1]
Test Clock – This input provides a clock for on-board test logic (JTAG). Development Serial Clock – This input line is the clock for the debug port interface. SECTION 21 DEVELOPMENT SUPPORT for details. 2.3.1.34 TDO/DSDO Pin Name: tdo_dsdo MPC555 MPC556 SIGNAL DESCRIPTIONS MOTOROLA USER’S MANUAL Rev. 15 October 2000...
Page 78: Trst
Pin Name: extclk EXTCLK – Input. This is the external frequency source for the chip. If this is unused, the pin must be grounded. 2.3.1.41 VDDSYN Pin Name: vddsyn MPC555 MPC556 SIGNAL DESCRIPTIONS MOTOROLA USER’S MANUAL Rev. 15 October 2000...
Page 79: Vsssyn
QSPI in master mode, and serial data output from the QSPI in slave mode. QGPIO[4] – When this pin is not needed for a QSPI application it can be configured as a general purpose input/output. MPC555 MPC556 SIGNAL DESCRIPTIONS MOTOROLA USER’S MANUAL...
Page 80: Mosi/Qgpio[5]
1, these pins can not function as general purpose inputs. 2.3.2.8 ECK Pin Name: eck External Baud Clock – This signal provides an external baud clock used by SCI1 and SCI2. MPC555 MPC556 SIGNAL DESCRIPTIONS MOTOROLA USER’S MANUAL Rev.
Page 81: Mios Pads
MIOS GPIO – This function allows the pins to be used as general-purpose inputs/out- puts. 2.3.3.6 VFLS[0:1]/MPIO32B[3:4] Pin Name: vfls0_mpio32b3 - vfls1_mpio32b4 (2 pins) MPC555 MPC556 SIGNAL DESCRIPTIONS MOTOROLA USER’S MANUAL Rev.
Page 82: Mpio32B[5:15]
Pin Name: a_an0_anw_pqb0 (1 pin for first QADC), b_an0_anw_pqb0 (1 pin for sec- ond QADC) Analog Channel (AN0) – Internally multiplexed input-only analog channels. Passed on as a separate signal to the QADC. Multiplexed Analog Input (ANW) – Externally multiplexed analog input. MPC555 MPC556 SIGNAL DESCRIPTIONS MOTOROLA USER’S MANUAL Rev.
Page 83: An[1]/Anx/Pqb[1]_[A:b]
Analog Input (AN[48:51]) – Analog input channel. The input is passed on as a sepa- rate signal to the QADC. Port (PQB[4:7]) – Input-only port. Has a synchronizer with an input enable and clock. The input is level-shifted before it is sent internally to the QADC. MPC555 MPC556 SIGNAL DESCRIPTIONS MOTOROLA USER’S MANUAL...
Page 84: An[52:54]/Ma[0:2]/Pqa[0:2]_[A:b]
VSSA – Input. Ground level for analog subsystems of the QADC_A and QADC_B modules. 2.3.6 TOUCAN_A/TOUCAN_B PADS 2.3.6.1 CNTX0_[A:B] Pin Name: a_cntx0 (1 pin for first CAN), b_cntx0 (1 pin for second CAN) MPC555 MPC556 SIGNAL DESCRIPTIONS MOTOROLA USER’S MANUAL Rev.
Page 85: Cnrx0_[A:b]
2.3.8 GLOBAL POWER SUPPLIES 2.3.8.1 VDDL Pin Name: vddl VDDL – 3-V voltage supply input. 2.3.8.2 VDDH Pin Name: vddh VDDH – 5-V voltage supply input. MPC555 MPC556 SIGNAL DESCRIPTIONS MOTOROLA USER’S MANUAL Rev. 15 October 2000 2-27 For More Information On This Product,...
Page 86: Vddi
Word. The 3-V related pins have selectable output buffer drive strengths which are controlled by the COM[0] bit in the USIU’s system clock and reset control register (SCCR). The control is as follows: MPC555 MPC556 SIGNAL DESCRIPTIONS MOTOROLA USER’S MANUAL Rev.
Page 87: Pad Module Configuration Register (Pdmcr)
SGPIO and all pads related to IMB modules. Table 2-4 illustrates which pins are affected by PRDS PRDS. 0 = Enable pull-up/pull-down devices 1 = Disable pull-up/pull-down devices MPC555 MPC556 SIGNAL DESCRIPTIONS MOTOROLA USER’S MANUAL Rev. 15 October 2000 2-29 For More Information On This Product, Go to: www.freescale.com...
Page 88: Pin State During Reset
For 5-V only pins, the enabling and disabling of the pull-up and pull-down devices is controlled by the PRDS bit in PDMCR. If the bit is negated, the devices are active. If the bit is asserted, the devices are inactive. MPC555 MPC556 SIGNAL DESCRIPTIONS MOTOROLA USER’S MANUAL...
Page 89: Pull-Up And Pull-Down Enable And Disable For 3-V / 5-V Multiplexed Pins
This causes the pull-up to be enabled. At the end of reset, the 3-V / 5-V select line goes low. This causes the pull-up to be disabled, preventing any power loss if the MCU starts fetching from external memory immediately out of reset. MPC555 MPC556 SIGNAL DESCRIPTIONS MOTOROLA USER’S MANUAL...
Page 90: Special Pull Resistor Disable Control (Sprds)
SPRDS is asserted. This disables the pull-up resistor immediately. The output driver drives the pin to the required state after reset. 2.4.8 Pin Reset States Table 2-4 summarizes the reset states of all the pins on the MPC555 / MPC556. Table 2-4 Pin Reset State Function Port...
Page 91 SGPIOC[6] PU5 until PRDS is set SGPIOC[6]/ FRZ/ PU5 until reset negates PU5 until reset negates MPC555 MPC556 SIGNAL DESCRIPTIONS MOTOROLA USER’S MANUAL Rev. 15 October 2000 2-33 For More Information On This Product,...
Page 92 XTAL — XTAL EXTAL — EXTAL — CLKOUT CLKOUT — EXTCLK — EXTCLK ENGCLK — ENGCLK/ BUCLK BUCLK — MPC555 MPC556 SIGNAL DESCRIPTIONS MOTOROLA USER’S MANUAL Rev. 15 October 2000 2-34 For More Information On This Product, Go to: www.freescale.com...
Page 93 PQB1 PU5 until PRDS is set PU5 until PRDS is set A: AN2/ANY/PQB2 PU5 until PRDS is set PQB2 PU5 until PRDS is set MPC555 MPC556 SIGNAL DESCRIPTIONS MOTOROLA USER’S MANUAL Rev. 15 October 2000 2-35 For More Information On This Product,...
Page 94 B_CNTX0 PU5 until PRDS is set A: CNRX0 A_CNRX0 PU5 until PRDS is set B: CNRX0 B_CNRX0 PU5 until PRDS is set MPC555 MPC556 SIGNAL DESCRIPTIONS MOTOROLA USER’S MANUAL Rev. 15 October 2000 2-36 For More Information On This Product,...
Page 95: Pad Types
• Output enable (OE) – Enables the output driver. For 3-V / 5-V pads, the appropri- ate driver is enabled based on the pin functionality selected. • Input enable – Enables the receiver. For 3-V / 5-V pads, the appropriate receiver is enabled based on the pin functionality selected. MPC555 MPC556 SIGNAL DESCRIPTIONS MOTOROLA USER’S MANUAL...
Page 96: Three-Volt Output Pad
OE. For a totem pole (push pull) pin with no three-state drive time, the OE can be connected to VDD, indicating a continuous drive. For a continuous drive, the pull-up can be disabled. MPC555 MPC556 SIGNAL DESCRIPTIONS MOTOROLA USER’S MANUAL...
Page 97: Type B Interface (Clock Pad)
Figure 2-4 Type B Interface 2.5.3 Three-Volt Input Pad Four subtypes are defined for the 3-V input-only pad: one with a pull-up resistor, one with a pull-up resistor and with or without hysteresis in the receiver, one with hysteresis MPC555 MPC556 SIGNAL DESCRIPTIONS MOTOROLA USER’S MANUAL...
Page 98: Type C Interface
Pad type CH has a 3-V input with hysteresis and a pull-up resistor. The hyst_sel signal selects the receiver with or without hysteresis. Data In Receiver Sprds hyst_sel Figure 2-6 Type CH Interface MPC555 MPC556 SIGNAL DESCRIPTIONS MOTOROLA USER’S MANUAL Rev. 15 October 2000 2-40 For More Information On This Product, Go to: www.freescale.com...
Page 99: Type Cnh Interface
This is a 3-V bi-directional pad with a pull-up device. The drive strength for the output driver can be configured for either a 25-pF or a 50-pF load. The SPRDS and OE sig- nals control the pull-up devices. MPC555 MPC556 SIGNAL DESCRIPTIONS MOTOROLA USER’S MANUAL...
Page 100: Type E Interface
2.5.4.2 Type EOH Interface In this pad type the data interface to the internal logic has separate paths for input and output. The receiver has hysteresis. The pull-up is active when the driver is not en- abled. MPC555 MPC556 SIGNAL DESCRIPTIONS MOTOROLA USER’S MANUAL...
Page 101: Type F Interface
Figure 2-10 3-V Type EOH Interface 2.5.4.3 Type F Interface In this pad type the data interface to the internal logic has the same path for both input and output. The pull-up is inactive when the driver is enabled. MPC555 MPC556 SIGNAL DESCRIPTIONS MOTOROLA USER’S MANUAL...
Page 102: Type G Interface
In this pad type the data interface to the internal logic has the same path for both input and output. This pad type also has the SPRDS signal as an input to disable the resistor when the pad is a non-bus function. MPC555 MPC556 SIGNAL DESCRIPTIONS MOTOROLA USER’S MANUAL...
Page 103: Five-Volt Input/Output Pad
If only one of the output paths is used on a device, the other can be connected to ground. In this case, the 3-V / 5-V select signal must be tied to the appropriate value to disable the other path. MPC555 MPC556 SIGNAL DESCRIPTIONS MOTOROLA USER’S MANUAL...
Page 104: Type I Interface
This pad has logic for a 3-V input/output function as well as a 5-V input/output function. A “3-V / 5-V sel” interface signal indicates which driver gets selected.The data inter- face to the internal logic has separate paths for input and output. MPC555 MPC556 SIGNAL DESCRIPTIONS MOTOROLA USER’S MANUAL...
Page 105: Type Ih Interface
In this pad type the data interface to the internal logic has separate paths for input and output. The 3-V receiver has 2 possible paths: with or without hysteresis. The hyst_sel signal selects the appropriate path. MPC555 MPC556 SIGNAL DESCRIPTIONS MOTOROLA USER’S MANUAL...
Page 106: Type J Interface
This pad has logic for a 3-V input/output function as well as a 5-V input/output function. A “3-V / 5-V sel” interface signal indicates which driver gets selected. The data inter- face to the internal logic has the same path for both input and output. MPC555 MPC556 SIGNAL DESCRIPTIONS MOTOROLA USER’S MANUAL...
Page 107: Type Jd Interface
A “3-V / 5-V sel” interface signal indicates which driver gets selected. The data interface to the internal logic has the same path for both input and output. The pad has a pull-down resistor which is activated by reset and/or PRDS. MPC555 MPC556 SIGNAL DESCRIPTIONS MOTOROLA USER’S MANUAL...
Page 108: Type K Interface (Epee Pad)
The synchronizer clock to this pad is GCLK2. MPC555 MPC556 SIGNAL DESCRIPTIONS MOTOROLA USER’S MANUAL...
Page 109: Analog Pads
This pad is used for interfacing to the port A of the QADC. The digital portion of the pad supports bi-directional operation. The receiver has a synchronizer. The digital in- put is level-shifted from 5 V to 3 V before it is sent internally to the QADC. MPC555 MPC556 SIGNAL DESCRIPTIONS MOTOROLA USER’S MANUAL...
Page 110: Type M Interface (Qadc Port B)
Analog In Analog PRDS Dig. In Level Synch. Rx Input Enable Shifter Sync. Clk Digital Figure 2-20 Type M Interface MPC555 MPC556 SIGNAL DESCRIPTIONS MOTOROLA USER’S MANUAL Rev. 15 October 2000 2-52 For More Information On This Product, Go to: www.freescale.com...
Page 111: Type N Interface (Etrig)
When the pin is an input, the data can be driven either synchronously or asynchronously. A pull-up device is available which can be disabled using the PRDS signal. MPC555 MPC556 SIGNAL DESCRIPTIONS MOTOROLA USER’S MANUAL...
Page 112: Type P Interface (Tpu And Mios Pads)
EPEE pad) to check for a state on the pin for a particular number of clocks. The pad also has a pull-up device. Depending on the reset state (see Table 2-4) the pull-up may be controlled by the PRDS signal. MPC555 MPC556 SIGNAL DESCRIPTIONS MOTOROLA USER’S MANUAL Rev.
Page 113: Input, 5V Output Pads
This pad is a 5-V output-only pad with slow and fast drive capability. The driver is con- figureable to be either push pull or open drain using the OD enable signal. This pad type has a pull-up device that can be controlled using the PRDS signal. MPC555 MPC556 SIGNAL DESCRIPTIONS MOTOROLA USER’S MANUAL...
Page 114: Type R Interface
A pull-up device can be controlled using the PRDS signal. PRDS Normal Receiver Data In Synch. Data In Synch. Receiver Synch. Clk Figure 2-25 Type R Interface MPC555 MPC556 SIGNAL DESCRIPTIONS MOTOROLA USER’S MANUAL Rev. 15 October 2000 2-56 For More Information On This Product, Go to: www.freescale.com...
Page 115: Output For Clock Pad
ADDR[8:31]/SGPIOA[8:31] IRQ[0]/SGPIOC[0], IRQ[1]/SGPIOC[1], IRQ[4]/SGPIOC[4] IRQ[2]/SGPIOC[2], IRQ[3]/SGPIOC[3], IRQ[5]/SGPIOC[5] All pins that drive 3 V have the provision to choose between drive strengths for a 25- pF load or a 50-pF load. MPC555 MPC556 SIGNAL DESCRIPTIONS MOTOROLA USER’S MANUAL Rev. 15 October 2000...
Page 116: Pin Names And Abbreviations
The following table lists the recommended abbreviations for all the pins on the MPC555 / MPC556. The abbreviations can be used in applications for which the actual name is too long. For example, they can be used to on circuit boards to map the pin location on the boards.
Page 117 IRQ[3]/KR, RETRY/SGPIOC[3] irq3_b_kr_b_retry_b_sgpioc3 irq3b_sgp IRQ[4]/AT[2]/SGPIOC[4] irq4_b_at2_sgpioc4 irq4b_sgp IRQ[5]/SGPIOC[5]/MODCK[1] irq5_b_sgpioc5_modck1 irq5b_sgp irq6_b_modck2 irq6b_mck2 IRQ[6:7]/MODCK[2:3] irq7_b_modck3 irq7b_mck3 tsiz0 tsiz0 TSIZ[0:1] tsiz1 tsiz1 MPC555 MPC556 SIGNAL DESCRIPTIONS MOTOROLA USER’S MANUAL Rev. 15 October 2000 2-59 For More Information On This Product, Go to: www.freescale.com...
Page 118 EXTAL extal extal CLKOUT clkout clkout EXTCLK extclk extclk VDDSYN vddsyn vddsyn VSSSYN vsssyn vsssyn ENGCLK/BUCLK engclk_buclk eck_buck MPC555 MPC556 SIGNAL DESCRIPTIONS MOTOROLA USER’S MANUAL Rev. 15 October 2000 2-60 For More Information On This Product, Go to: www.freescale.com...
Page 119 VF[0:2]/MPIO32B[0:2] vf1_mpio32b1 vf1_mpio1 vf2_mpio32b2 vf2_mpio2 vfls0_mpio32b3 vfls0_mpio3 VFLS[0:1]/MPIO32B[3:4] vfls1_mpio32b4 vfls1_mpio4 MPC555 MPC556 SIGNAL DESCRIPTIONS MOTOROLA USER’S MANUAL Rev. 15 October 2000 2-61 For More Information On This Product, Go to: www.freescale.com...
Page 120 A: T2CLK a_t2clk a_t2clk MPC555 MPC556 SIGNAL DESCRIPTIONS MOTOROLA USER’S MANUAL Rev. 15 October 2000 2-62 For More Information On This Product, Go to: www.freescale.com...
Page 121 B: AN0/ANW/PQB0 b_an0_anw_pqb0 ban0_pqb0 B: AN1/ANX/PQB1 b_an1_anx_pqb1 ban1_pqb1 B: AN2/ANY/PQB2 b_an2_any_pqb2 ban2_pqb2 B: AN3/ANZ/PQB3 b_an3_anz_pqb3 ban3_pqb3 MPC555 MPC556 SIGNAL DESCRIPTIONS MOTOROLA USER’S MANUAL Rev. 15 October 2000 2-63 For More Information On This Product, Go to: www.freescale.com...
Page 122 VDDSRAM vddsram vddsram J9, J10, J11, J12, K9, K10, K11, K12, L9, L10, L11, L12, M9, M10, M11, M12 MPC555 MPC556 SIGNAL DESCRIPTIONS MOTOROLA USER’S MANUAL Rev. 15 October 2000 2-64 For More Information On This Product, Go to: www.freescale.com...
Page 123: Central Processing Unit
(LSU), and a branch processing unit (BPU), floating-point unit (FPU) and in- teger multiplier divider (IMD). The use of simple instructions with rapid execution times yields high efficiency and throughput for MPC555 / MPC556-based systems. Most integer instructions execute in one clock cycle. Instructions can complete out of order for increased performance;...
Page 124: Rcpu Block Diagram
NEXT ADDRESS CONTROL GENERATION REGS WRI TE BAC K B US 2 SL OT S/ CL OC K Figure 3-1 RCPU Block Diagram MPC555 MPC556 CENTRAL PROCESSING UNIT MOTOROLA USER’S MANUAL Rev. 15 October 2000 For More Information On This Product,...
Page 125: Instruction Sequencer
Instructions issued beyond a predicted branch do not complete execution until the branch is resolved, preserving the programming model of sequential execution. If branch prediction is incorrect, the instruction unit flushes all predicted path instruc- tions, and instructions are issued from the correct path. MPC555 MPC556 CENTRAL PROCESSING UNIT MOTOROLA USER’S MANUAL...
Page 126: Independent Execution Units
For example, since branch instructions do not depend on GPRs, branches can often be resolved early, eliminating stalls caused by taken branches. Table 3-1 summarizes the RCPU execution units. MPC555 MPC556 CENTRAL PROCESSING UNIT MOTOROLA USER’S MANUAL Rev.
Page 127: Branch Processing Unit (Bpu)
• The IMUL–IDIV unit includes the implementation of the integer multiply and divide instructions. • The ALU–BFU unit includes the implementation of all integer logic, add and sub- tract, and bit field instructions. MPC555 MPC556 CENTRAL PROCESSING UNIT MOTOROLA USER’S MANUAL Rev.
Page 128: Load/Store Unit (Lsu)
MPC556 to efficiently implement floating-point operations such as multiply, multiply- add, and divide. The MPC555 / MPC556 depends on a software envelope to fully implement the IEEE floating-point specification. Overflows, underflows, NaNs, and denormalized numbers cause floating-point assist exceptions that invoke a software routine to deliver (with hardware assistance) the correct IEEE result.
Page 129: Levels Of The Powerpc Architecture
(that is, through the use of specific instructions for that purpose such as move to spe- cial-purpose register (mtspr) and move from special-purpose register (mfspr) instruc- tions) or implicitly as the part of the execution of an instruction. Some registers are accessed both explicitly and implicitly. MPC555 MPC556 CENTRAL PROCESSING UNIT MOTOROLA USER’S MANUAL...
Page 130: Rcpu Programming Model
USER MODEL VEA Time Base Facility (for Reading) Time Base Lower – Read (TBL) Time Base Upper – Read (TBU) Figure 3-3 RCPU Programming Model Table 3-2 lists the MPC555 / MPC556 supervisor-level registers. MPC555 MPC556 CENTRAL PROCESSING UNIT MOTOROLA USER’S MANUAL Rev.
Page 131 L2U Global Region Attribute (L2U_GRA)1 Table 11-10 for bit descriptions. BBC Module Configuration Register (BBCMCR)1 Table 4-8 for bit descriptions. MPC555 MPC556 CENTRAL PROCESSING UNIT MOTOROLA USER’S MANUAL Rev. 15 October 2000 For More Information On This Product,...
Page 132 Floating-Point Exception Cause Register (FPECR)1 1022 3.9.10.2 Floating-Point Exception Cause Register (FPECR) for bit descriptions. NOTES: 1. Implementation-specific SPR. Table 3-3 lists the MPC555 / MPC556 SPRs used for development support. MPC555 MPC556 CENTRAL PROCESSING UNIT MOTOROLA USER’S MANUAL Rev. 15 October 2000 3-10 For More Information On This Product, Go to: www.freescale.com...
Page 133: Powerpc Uisa Register Set
3.7 PowerPC UISA Register Set The PowerPC UISA registers can be accessed by either user- or supervisor-level in- structions. The general-purpose registers are accessed through instruction operands. MPC555 MPC556 CENTRAL PROCESSING UNIT MOTOROLA USER’S MANUAL...
Page 134: General-Purpose Registers (Gprs)
3.7.3 Floating-Point Status and Control Register (FPSCR) The FPSCR controls the handling of floating-point exceptions and records status re- sulting from the floating-point operations. FPSCR[0:23] are status bits. FPSCR[24:31] are control bits. MPC555 MPC556 CENTRAL PROCESSING UNIT MOTOROLA USER’S MANUAL Rev.
Page 135 RESET: UNCHANGED FPRF[1:4] VXCVI SOFT SQRT RESET: UNCHANGED A listing of FPSCR bit descriptions is shown in Table 3-5. MPC555 MPC556 CENTRAL PROCESSING UNIT MOTOROLA USER’S MANUAL Rev. 15 October 2000 3-13 For More Information On This Product, Go to: www.freescale.com...
Page 136 Floating-point less than or negative (FL or <) Floating-point greater than or positive (FG or >) Floating-point equal or zero (FE or =) Floating-point unordered or NaN (FU or ?) — Reserved MPC555 MPC556 CENTRAL PROCESSING UNIT MOTOROLA USER’S MANUAL Rev. 15 October 2000...
Page 137 The condition register (CR) is a 32-bit register that reflects the result of certain opera- tions and provides a mechanism for testing and branching. The bits in the CR are grouped into eight 4-bit fields, CR0 to CR7. MPC555 MPC556 CENTRAL PROCESSING UNIT MOTOROLA USER’S MANUAL...
Page 138: Condition Register Cr0 Field Definition
For more information about the FPSCR, 3.7.3 Floating-Point Status and Control Register (FPSCR). The bit descriptions for the CR1 field are shown in Table 3-8. MPC555 MPC556 CENTRAL PROCESSING UNIT MOTOROLA USER’S MANUAL Rev. 15 October 2000...
Page 139: Condition Register Crn Field - Compare Instruction
XER — Integer Exception Register SPR 1 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Reserved BYTES RESET: MPC555 MPC556 CENTRAL PROCESSING UNIT MOTOROLA USER’S MANUAL Rev. 15 October 2000...
Page 140: Link Register (Lr)
LR — Link Register SPR 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Branch Address RESET: UNCHANGED MPC555 MPC556 CENTRAL PROCESSING UNIT MOTOROLA USER’S MANUAL Rev.
Page 141: Count Register (Ctr)
The PowerPC VEA includes the time base facility (TB), a 64-bit structure that contains a 64-bit unsigned integer that is incremented periodically. The frequency at which the counter is updated is implementation-dependent. For details on the time base clock in the MPC555 / MPC556, refer to 6.7 MPC555 / MPC556 Time Base (TB), 8.6 MPC555...
Page 142: Powerpc Oea Register Set
1. Reset value of this bit depends on the value of the internal data bus line during reset. 2. This bit is only available on the MPC556. Table 3-12 shows the bit definitions for the MSR. MPC555 MPC556 CENTRAL PROCESSING UNIT MOTOROLA USER’S MANUAL...
Page 143 Data relocation 0 = Data address translation is off, the L2U DMPU does not check for address permission at- tributes. 1 = Data address translation is on, the L2U DMPU checks for address permission attributes. MPC555 MPC556 CENTRAL PROCESSING UNIT MOTOROLA USER’S MANUAL...
Page 144: Dae/Source Instruction Service Register (Dsisr)
DAR — Data Address Register SPR 19 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Data Address RESET: UNCHANGED MPC555 MPC556 CENTRAL PROCESSING UNIT MOTOROLA USER’S MANUAL Rev.
Page 145: Time Base Facility (Tb) - Oea
3.9.5 Decrementer Register (DEC) The decrementer (DEC, SPR 22) is a 32-bit decrementing counter defined by the MPC555 / MPC556 to provide a decrementer exception after a programmable delay. The DEC satisfies the following requirements: • Loading a GPR from the DEC has no effect on the DEC.
Page 146: Machine Status Save/Restore Register 0 (Srr0)
Freescale Semiconductor, Inc. clock in the MPC555 / MPC556, refer to 6.6 MPC555 / MPC556 Decrementer, MPC555 / MPC556 Internal Clock Signals, and 8.12.1 System Clock Control Reg- ister (SCCR). The DEC does not run after power-up and must be enabled by setting the TBE bit in...
Page 147: General Sprs (Sprg0-Sprg3)
SPR 287 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 VERSION REVISION RESET: UNCHANGED MPC555 MPC556 CENTRAL PROCESSING UNIT MOTOROLA USER’S MANUAL Rev. 15 October 2000...
Page 148: Implementation-Specific Sprs
MPC555 / MPC556 value is 0x0020. 3.9.10 Implementation-Specific SPRs The MPC555 / MPC556 includes several implementation-specific SPRs that are not defined by the PowerPC architecture. These registers can be accessed by supervisor- level instructions only. These registers are listed in...
Page 149: Additional Implementation-Specific Registers
NOTE Software must insert a sync instruction before reading the FPECR. 3.9.10.3 Additional Implementation-Specific Registers Refer to the following sections for details on additional implementation-specific regis- ters in the MPC555 / MPC556: • 4.6 Burst Buffer Programming Model • 6.13.1.2 Internal Memory Map Register •...
Page 150: Instruction Set
The PowerPC architecture uses instructions that are four bytes long and word-aligned. It provides for byte, half-word, and word operand loads and stores between memory and a set of 32 GPRs. MPC555 MPC556 CENTRAL PROCESSING UNIT MOTOROLA USER’S MANUAL...
Page 151: Instruction Set Summary
Condition Register Equivalent crnand crbD,crbA,crbB Condition Register NAND crnor crbD,crbA,crbB Condition Register NOR cror crbD,crbA,crbB Condition Register OR MPC555 MPC556 CENTRAL PROCESSING UNIT MOTOROLA USER’S MANUAL Rev. 15 October 2000 3-29 For More Information On This Product, Go to: www.freescale.com...
Page 152 Load Byte and Zero Indexed frD,d(rA) Load Floating-Point Double lfdu frD,d(rA) Load Floating-Point Double with Update MPC555 MPC556 CENTRAL PROCESSING UNIT MOTOROLA USER’S MANUAL Rev. 15 October 2000 3-30 For More Information On This Product, Go to: www.freescale.com...
Page 153 SPR,rS Move to Special Purpose Register mulhw (mulhw.) rD,rA,rB Multiply High Word mulhwu (mulhwu.) rD,rA,rB Multiply High Word Unsigned MPC555 MPC556 CENTRAL PROCESSING UNIT MOTOROLA USER’S MANUAL Rev. 15 October 2000 3-31 For More Information On This Product, Go to: www.freescale.com...
Page 154 Store Multiple Word stswi rS,rA,NB Store String Word Immediate stswx rS,rA,rB Store String Word Indexed rS,d(rA) Store Word MPC555 MPC556 CENTRAL PROCESSING UNIT MOTOROLA USER’S MANUAL Rev. 15 October 2000 3-32 For More Information On This Product, Go to: www.freescale.com...
Page 155: Recommended Simplified Mnemonics
• EA = (rA|0) + rB (register indirect with index) These simple addressing modes allow efficient address generation for memory ac- cesses. Calculation of the effective address for aligned transfers occurs in a single clock cycle. MPC555 MPC556 CENTRAL PROCESSING UNIT MOTOROLA USER’S MANUAL...
Page 156: Exception Model
Synchronous (ordered, precise) Instruction-caused exceptions 3.11.2 Ordered Exceptions In the MPC555 / MPC556, all exceptions except for reset, debug port non-maskable interrupts, and machine check exceptions are ordered. Ordered exceptions satisfy the following criteria: • Only one exception is reported at a time. If, for example, a single instruction en- counters multiple exception conditions, those conditions are encountered se- quentially.
Page 157: Precise Exceptions
NOTE In the MPC555 / MPC556, the exception table can additionally be re- located by the BBC module to internal memory and reduce the total size required by the exception table (see 4.5 Exception Table Relo-...
Page 158: Instruction Timing
Implementation-dependent non-maskable external breakpoint 3.12 Instruction Timing The MPC555 / MPC556 processor is pipelined. Because the processing of an instruc- tion is broken into a series of stages, an instruction does not require the entire resourc- es of the processor.
Page 159: Basic Instruction Pipeline
Note that when the blockage equals the latency, it is not pos- sible to issue another instruction to the same unit in the same cycle in which the first instruction is being written back. MPC555 MPC556 CENTRAL PROCESSING UNIT MOTOROLA USER’S MANUAL...
Page 160: Powerpc User Instruction Set Architecture (Uisa)
3.13 PowerPC User Instruction Set Architecture (UISA) 3.13.1 Computation Modes The core of the MPC555 / MPC556 is a 32-bit implementation of the PowerPC archi- tecture. Any reference in the PowerPC Architecture Books (UISA, VEA, OEA) regard- ing 64-bit implementations are not supported by the core. All registers except the floating-point registers are 32 bits wide.
Page 161: Exceptions
3.13.7.1 Invalid Branch Instruction Forms Bits marked with z in the BO encoding definition are discarded by the MPC555 / MPC556 decoding. Thus, these types of invalid form instructions yield result of the de- fined instructions with the z bit zero. If the decrement and test CTR option is specified for the bcctr or bcctrl instructions, the target address of the branch is the new value of the CTR.
Page 162: Floating-Point Processor
1 is identical to the valid form instruction with L = 0 3.13.9 Floating-Point Processor 3.13.9.1 General The MPC555 / MPC556 implements all floating-point features as defined in the UISA, including the non-IEEE working mode. Some features require software assistance. For more information refer to RCPU Reference Manual (Floating-point Load Instruc- tions) for more information.
Page 163: Fixed-Point Load With Update And Store With Update Instructions
In case the operand falls in the range of double denormalized numbers it is considered a programming error. The hardware will handle this case as if the operand was ZERO. MPC555 MPC556 CENTRAL PROCESSING UNIT MOTOROLA USER’S MANUAL...
Page 164: Optional Instructions
The effect of operand placement on performance is as stated in the VEA, except for the case of 8- byte operands. In that case, since the MPC555 / MPC556 uses a 32-bit wide data bus, the performance is good rather than optimal.
Page 165: Enforce In-Order Execution Of I/O (Eieio) Instruction
The MPC555 / MPC556 has an internal memory space that includes memory-mapped control registers and internal memory used by various modules on the chip. This mem- ory is part of the main memory as seen by the MPC555 / MPC556 but cannot be ac- cessed by any external system master.
Page 166: Storage Control Instructions
3-3. 3.15.3 Storage Control Instructions Storage Control Instructions mtsr, mtsrin, mfsr, mfsrin, dcbi, tlbie, tlbia, and tlb- sync are not implemented by the MPC555 / MPC556. 3.15.4 Interrupts The core implements all storage-associated interrupts as precise interrupts. This means that a load/store instruction is not complete until all possible error indications have been sampled from the load/store bus.
Page 167: Machine Check Interrupt
= 1. If = 0 and a machine check interrupt indication is received, the processor enters the checkstop state. The behavior of the MPC555 / MPC556 in checkstop state is de- pendent on the working mode as defined in 21.4.1.1 Debug Mode Enable vs. Debug Mode Disable.
Page 168: Instruction Storage Interrupt
) is set, the floating-point assist interrupt is generated. 3.15.4.7 Illegal Instruction Type Program Interrupt An illegal instruction type program interrupt is not generated by the MPC555 / MPC556. An implementation dependent software emulation interrupt is generated in- stead. 3.15.4.8 Privileged Instruction Type Program interrupt...
Page 169: Floating-Point Unavailable Interrupt
Freescale Semiconductor, Inc. 3.15.4.9 Floating-Point Unavailable Interrupt The floating-point unavailable interrupt is generated by the MPC555 / MPC556 core as defined in the OEA. 3.15.4.10 Trace Interrupt A trace interrupt occurs if MSR = 1 and any instruction except rfi is successfully com- pleted or MSR = 1 and a branch is completed.
Page 170: Implementation-Dependent Software Emulation Interrupt
• Floating-point enabled exception type program interrupt is not generated by float- ing-point arithmetic instructions, instead if ((MSR | MSR ) &FPSCR ) is set, the floating-point assist interrupt is generated. In addition, the following registers are set: MPC555 MPC556 CENTRAL PROCESSING UNIT MOTOROLA USER’S MANUAL Rev. 15 October 2000 3-48 For More Information On This Product, Go to: www.freescale.com...
Page 171: Implementation-Specific Instruction Storage Protection Error Interrupt
The implementation-specific instruction storage protection error interrupt occurs in the following cases: • The fetch access violates storage protection. • The fetch access is to guarded storage and MSR = 1. The following registers are set: MPC555 MPC556 CENTRAL PROCESSING UNIT MOTOROLA USER’S MANUAL Rev. 15 October 2000...
Page 172: Implementation-Specific Data Storage Protection Error Interrupt
3.15.4.14 Implementation-Specific Data Storage Protection Error Interrupt The implementation-specific data storage protection error interrupt occurs in the fol- lowing case: • The access violates the storage protection. The following registers are set: MPC555 MPC556 CENTRAL PROCESSING UNIT MOTOROLA USER’S MANUAL Rev.
Page 173: Implementation-Specific Debug Interrupts
• When there is an internal breakpoint match (for more details, refer to SECTION 21 DEVELOPMENT SUPPORT. • When a peripheral breakpoint request is asserted to the MPC555 / MPC556 core. • When the development port request is asserted to the MPC555 / MPC556 core. Refer to SECTION 21 DEVELOPMENT SUPPORT for details on how to generate the development port-interrupt request.
Page 174: Partially Executed Instructions
In the MPC555 / MPC556, the instruction can be partially ex- ecuted only in the case of the load/store instructions that cause multiple access to the memory subsystem.
Page 175: Timer Facilities
3.15.6 Optional Facilities and Instructions Any other OEA optional facilities and instructions (except those that are discussed here) are not implemented by the MPC555 / MPC556 hardware. Attempting to execute any of these instructions causes an implementation dependent software emulation in- terrupt to be taken.
Page 176 Freescale Semiconductor, Inc. MPC555 MPC556 CENTRAL PROCESSING UNIT MOTOROLA USER’S MANUAL Rev. 15 October 2000 3-54 For More Information On This Product, Go to: www.freescale.com...
Page 177: Burst Buffer
The IMPU does not support address translation. The effective fetch address issued by the processor is the one that is transferred to the U-bus. 4.1 Burst Buffer Block Diagram Figure 4-1 is a block diagram of the burst buffer. MPC555 / MPC556 BURST BUFFER MOTOROLA USER’S MANUAL Rev. 15 October 2000 For More Information On This Product, Go to: www.freescale.com...
Page 178: Burst Buffer Features
• Supports program trace and show cycle attributes. • Supports special attribute for debug port fetch accesses. • Is programmed using the MPC555 / MPC556 mtspr/mfspr instructions to/from implementation specific special-purpose registers. • Designed for minimum power consumption.
Page 179: Instruction Vocabularybased Compression Model Main Principles
• Interrupt generated upon access violation or fetch from guarded region. • MPC555 / MPC556 MSR[IR] bit controls MPU protection. • Programming is done using MPC555 / MPC556 mtspr/mfspr instructions to/from implementation specific special purpose registers. • Designed for minimum power consumption.
Page 180: Model Limitations
2. Compression of a combination of the instruction’s bytes into vocabulary point- ers and bypass of the other byte(s). Bypass is the placing of the field’s uncom- pressed instruction information into the compressed code. 3. Bypass of the whole instruction. No compaction permitted. MPC555 MPC556 BURST BUFFER MOTOROLA USER’S MANUAL...
Page 181: Example Of Compressed Code
This partitionong produced a better comression ratio. 23 24 vocabulary3 vocabulary4 vocabulary1 vocabulary2 Figure 4-3 Instruction Coding MPC555 MPC556 BURST BUFFER MOTOROLA USER’S MANUAL Rev. 15 October 2000 For More Information On This Product, Go to: www.freescale.com...
Page 182: Memory Organization
30 31 Instruction Code Base Address Left Bit Pointer Right Bit Pointer Figure 4-5 Two Streams Memory Organization — After Compression MPC555 MPC556 BURST BUFFER MOTOROLA USER’S MANUAL Rev. 15 October 2000 For More Information On This Product, Go to: www.freescale.com...
Page 183: Examples Of Compressed Symbols Layout
Boundary assumed to be 12 for both lines Xn,1 Xn,2 Xn+1,1 (n) and (n+1) are word addresses in the original uncompressed code Figure 4-6 Examples of Compressed Symbols Layout MPC555 MPC556 BURST BUFFER MOTOROLA USER’S MANUAL Rev. 15 October 2000 For More Information On This Product, Go to: www.freescale.com...
Page 184: Compressed Code Address Format
21 is one “1”, then the two parts of the instruction are located in different address word locations (one at “x” base address, the other at “x+4”). Figure 4-8 illustrates the three possible cases for bits 20 and 21. MPC555 MPC556 BURST BUFFER MOTOROLA USER’S MANUAL...
Page 185: Compressed Address Format - Direct Branches
The word pointer for the unconditional branch has nineteen bits (the lower two-byte bits are ignored). This will yield an uncon- ditional branch displacement limit of two Mbytes. The word pointer for the conditional MPC555 MPC556 BURST BUFFER MOTOROLA USER’S MANUAL...
Page 186 Calculator 5-bit Word Pointer - Base Address Pointer Direct (internal) branch address format (one pointer format) Figure 4-9 Generating Compressed Code Address for PowerPC Direct Branches MPC555 MPC556 BURST BUFFER MOTOROLA USER’S MANUAL Rev. 15 October 2000 4-10 For More Information On This Product,...
Page 187: Compressed Address Format - Indirect Branches
• User application code compression by software compression tool. The compiler will add a few simple “hooks” to the compiled code which will make com- pression possible. Compiled code will be generated in the “elf” format for code MPC555 MPC556 BURST BUFFER MOTOROLA USER’S MANUAL...
Page 188: Code Compression Process (Phase A)
Therefore, the instructions that occur most in code should be represented earlier in the vocabulary structure. This would produce the most condensed code. A statistical study was made of typical application code. The existing vocabulary is fixed for Phase A MPC555 MPC556 BURST BUFFER MOTOROLA USER’S MANUAL...
Page 189: Decompression
• When instructions are running without a COF, the next instruction is pre- fetched and decoded in the current cycle. This eliminates any delays from code compression during regular sequential (non-COF) operation. COF = Change of Flow MPC555 MPC556 BURST BUFFER MOTOROLA USER’S MANUAL...
Page 190: Compression Environment Initialization
• Normal • Slave • Reset • Debug • Standby • Burst The modes of operation are described in the following paragraphs. MPC555 MPC556 BURST BUFFER MOTOROLA USER’S MANUAL Rev. 15 October 2000 4-14 For More Information On This Product,...
Page 191: Normal Operation
4.4.6 Burst Operation The BBC can run burst accesses on the U-bus. Such burst cycles, if forwarded to ex- ternal memory, are then exported to the EBI as burst cycles (if bursts are enabled by the USIU). MPC555 MPC556 BURST BUFFER MOTOROLA USER’S MANUAL...
Page 192: Error Detection
MPC555 / MPC556 and requries MSR[IP] = 1. This feature is important in multi- MPC555 / MPC556 systems, where more than one MCU can have internal exception tables with the same exception addresses issued by the RCPU.
Page 193: Exception Table Relocation Operation
NOTE 1 The eight Kbytes allocated for the exception table can be almost fully utilized. This is possible if the MPC555 / MPC556’s address space is not mapped to the exception address space — that is, if addresses 0xFFF0_0000 to 0xFFF0_1FFF are not part of the MPC555 / MPC556 address space.
Page 194 3.11.5 Exception Vector Table for Exception Relocation Table with ETRE = 0. 2. See 4.6.4 BBC Module Configuration Register (BBCMCR) 3. The reset exception is NOT affected by OERC. MPC555 MPC556 BURST BUFFER MOTOROLA USER’S MANUAL Rev. 15 October 2000...
Page 195: Exception Table Entries Mapping
1F00 branch to... branch to... branch to... branch to... Main code can start here Figure 4-14 Exception Table Entries Mapping MPC555 MPC556 BURST BUFFER MOTOROLA USER’S MANUAL Rev. 15 October 2000 4-19 For More Information On This Product,...
Page 196: Burst Buffer Programming Model
Freescale Semiconductor, Inc. 4.6 Burst Buffer Programming Model The BBC and IMPU module configuration registers are MPC555 / MPC556 special- purpose registers (SPRs). They are programmed with the MPC555 / MPC556 mtspr/ mfspr instructions. All the registers can be accessed in supervisor mode only. The processor generates an exception internally if an attempt is made to access the registers from user mode.
Page 197: Region Base Address Registers
MI_RA[0:3] — Region Attribute Register SPR 816 – 819 HRESET RESERVED RESERVED CMPR ‘ HRESET NOTES: 1. Available only on the MPC556. MPC555 MPC556 BURST BUFFER MOTOROLA USER’S MANUAL Rev. 15 October 2000 4-21 For More Information On This Product, Go to: www.freescale.com...
Page 198 1. G and PP attributes perform similar protection activities on a region. The more protective attribute will be implied on the region if the attributes programming oppose each other. 2. This bit is available only on the MPC556. MPC555 MPC556 BURST BUFFER MOTOROLA USER’S MANUAL...
Page 199: Global Region Attribute Register Description (Mi_Gra)
11 = Region is considered a compressed code region. Access to the region is allowed only in "De-compression On" mode 28:31 — Reserved NOTES: 1. Available only on the MPC556. MPC555 MPC556 BURST BUFFER MOTOROLA USER’S MANUAL Rev. 15 October 2000 4-23 For More Information On This Product, Go to: www.freescale.com...
Page 200: Bbc Module Configuration Register (Bbcmcr)
#22. COMP 0 = The MPC556 assumes that exception routines are non-compressed 1 = The MPC556 assumes that ALL exception routines are compressed. This bit effects only when EN_COMP bit is set. MPC555 MPC556 BURST BUFFER MOTOROLA USER’S MANUAL Rev.
Page 201 1 = Decompression Show Cycles includes the bit pointer information on the data bus. 24:31 — Reserved NOTE An ISYNC instruction is required immediately following any write to the BBCMCR. MPC555 MPC556 BURST BUFFER MOTOROLA USER’S MANUAL Rev. 15 October 2000 4-25 For More Information On This Product, Go to: www.freescale.com...
Page 202 Freescale Semiconductor, Inc. MPC555 MPC556 BURST BUFFER MOTOROLA USER’S MANUAL Rev. 15 October 2000 4-26 For More Information On This Product, Go to: www.freescale.com...
Page 203: Module Overview
The MPC555 / MPC556 is designed to allow external bus masters to request and obtain mastership of the system bus, and if required access the on-chip memory and regis- ters.
Page 204: Siu Architecture
32 bits wide. The address shown for each register is relative to the base ad- dress of the MPC555 / MPC556 internal memory map. The internal memory block can reside in one of eight possible 4-Mbyte memory spaces. See...
Page 205 0x2F C118 Table 10-7 for bit descriptions. Option Register 3 (OR3) 0x2F C11C Table 10-8 for bit descriptions. MPC555 MPC556 UNIFIED SYSTEM INTERFACE UNIT MOTOROLA USER’S MANUAL Rev. 15 October 2000 For More Information On This Product, Go to: www.freescale.com...
Page 206 0x2F C288 Table 7-3 for bit descriptions. Change of Lock Interrupt Register (COLIR) 0x2F C28C Table 8-11 for bit descriptions. MPC555 MPC556 UNIFIED SYSTEM INTERFACE UNIT MOTOROLA USER’S MANUAL Rev. 15 October 2000 For More Information On This Product, Go to: www.freescale.com...
Page 207: Usiu Powerpc Memory Map
USIU PowerPC special-purpose registers (SPR). These registers can be accessed with the PowerPC mtspr and mfspr instructions, or from an external master (refer to 6.2 External Master Modes for details). All registers are 32 bits wide. MPC555 MPC556 UNIFIED SYSTEM INTERFACE UNIT MOTOROLA USER’S MANUAL Rev.
Page 208 SPR access is valid. Table 5-3 PowerPC Address Range 0:17 18:27 28:31 0 . . . 0 spr[0:9] 0000 MPC555 MPC556 UNIFIED SYSTEM INTERFACE UNIT MOTOROLA USER’S MANUAL Rev. 15 October 2000 For More Information On This Product, Go to: www.freescale.com...
Page 209 • Power-PC Time Base Counter (TB) — The TB is a 64-bit counter defined by the MPC555 / MPC556 architecture to provide a time base reference for the operat- ing system or application software. The TB has four independent reference reg- isters which can generate a maskable interrupt when the time-base counter reaches the value programmed in one of the four reference registers.
Page 210 This binary counter is clocked by the same frequency as the time base (also de- fined by the MPC555 / MPC556 architecture). The period for the DEC when driv- en by a 4-Mhz oscillator is 4295 seconds, which is approximately 71.6 minutes.
Page 211: Usiu Pins Multiplexing
6.13.1.1 SIU Module Configuration Register.) 6.1.2 Memory Mapping The MPC555 / MPC556 internal memory space can be assigned to one of eight loca- tions. The internal memory map is organized as a single 4-Mbyte block. The user can assign this block to one of eight locations by programming the ISB field in the internal memory...
Page 212: Arbitration Support
0x01C0 0000 0x01FF FFFF 0xFFFF FFFF Figure 6-2 MPC555 / MPC556 Memory Map 6.1.3 Arbitration Support Two bits in the SIUMCR control USIU bus arbitration. The external arbitration (EARB) bit determines whether arbitration is performed internally or externally. If EARB is cleared (internal arbitration), the external arbitration request priority (EARP) bit deter- mines the priority of an external master’s arbitration request.
Page 213: External Master Modes
The MPC555 / MPC556 does not support burst accesses from an external master; only single accesses of 8, 16, or 32 bits can be performed. The MPC555 / MPC556 asserts burst inhibit (BI) on any attempt to initiate a burst access to internal memory.
Page 214: Address Decoding For External Accesses
The external master may access the internal MPC555 / MPC556 special registers that are located outside the RCPU. In order to access one of these MPC555 / MPC556 reg- isters, program the EMCR to MPC555 / MPC556 special register access (CONT = 1 and SUPU = 0 in EMCR).
Page 215 1. SGPIOC[0:7] is selected according to GPC and MLRC fields in SIUMCR. See 6.13.1.1 SIU Module Configu- ration Register. Figure 6-3 illustrates the functionality of the SGPIO. MPC555 MPC556 SYSTEM CONFIGURATION AND PROTECTION MOTOROLA USER’S MANUAL Rev. 15 October 2000 For More Information On This Product, Go to: www.freescale.com...
Page 216: Interrupt Controller
The USIU receives interrupts from internal sources (such as the PIT and RTC), from the IMB3 module (which has its own interrupt controller), and from external pins IRQ[0:7]. An overview of the MPC555 / MPC556 interrupt structure is shown in Figure 6-4.
Page 217 Debug Debug IRQOUT Figure 6-4 MPC555 / MPC556 Interrupt Structure If programmed to generate interrupts, the SWT and external pin IRQ[0] always gener- ate a non-maskable interrupt (NMI) to the RCPU. Notice that the RCPU takes the sys- tem reset interrupt when an NMI is asserted and the external interrupt for any other interrupt asserted by the interrupt controller.
Page 218 If the same interrupt level is assigned to more than one source, soft- ware must read the appropriate status bits in the appropriate UIMB3 registers to determine which interrupt was asserted. Figure 6-5 illustrates the operation of the interrupt controller. MPC555 MPC556 SYSTEM CONFIGURATION AND PROTECTION MOTOROLA USER’S MANUAL Rev.
Page 219: Siu Interrupt Sources Priority
Interrupt Request (to RCPU and Pads) latch Figure 6-5 MPC555 / MPC556 Interrupt Configuration 6.4.1 SIU Interrupt Sources Priority The SIU has 15 interrupt sources that assert just one interrupt request to the RCPU. There are eight external IRQ pins (IRQ[0] should be masked since it generates a NMI) and eight interrupt levels.
Page 220: Hardware Bus Monitor
The decrementer (DEC) is a 32-bit decrementing counter defined by the MPC555 / MPC556 architecture to provide a decrementer interrupt. This binary counter is clocked by the same frequency as the time base (also defined by the MPC555 / MPC556 architecture). The operation of the time base and decrementer are therefore coherent.
Page 221: Mpc555 / Mpc556 Time Base (Tb)
3.9.5 Decrementer Register (DEC) for more information. 6.7 MPC555 / MPC556 Time Base (TB) The time base (TB) is a 64-bit free-running binary counter defined by the MPC555 / MPC556 architecture. The TB has two independent reference registers which can MPC555...
Page 222: Real-Time Clock (Rtc)
MPC555 / MPC556 architecture for read- ing and writing the time base. For the MPC555 / MPC556 implementation, it is not pos- sible to read or write the entire TB in a single instruction. Therefore, the mttb and mftb instructions are used to move the lower half of the time base (TBL) while the mttbu and mftbu instructions are used to move the upper half (TBU).
Page 223: Periodic Interrupt Timer (Pit)
PITC. If the PTE bit is not set, the PIT is unable to count and retains the old count value. Reads of the PIT have no effect on the counter value. MPC555 MPC556 SYSTEM CONFIGURATION AND PROTECTION MOTOROLA USER’S MANUAL...
Page 224: Software Watchdog Timer (Swt)
2. Write 0xAA39 to the SWSR The service sequence clears the watchdog timer and the timing process begins again. If any value other than 0x556C or 0xAA39 is written to the SWSR, the entire sequence must start over. MPC555 MPC556 SYSTEM CONFIGURATION AND PROTECTION MOTOROLA USER’S MANUAL...
Page 225 SWTC, the software watchdog timer is not updated until the ser- vicing sequence is written to the SWSR. If the SWE is loaded with the value zero, the modulus counter does not count. MPC555 MPC556 SYSTEM CONFIGURATION AND PROTECTION MOTOROLA USER’S MANUAL...
Page 226: Freeze Operation
MCU out of these low-power modes. 6.13 System Configuration and Protection Registers This section provides diagrams and bit descriptions of the system configuration and protection registers. MPC555 MPC556 SYSTEM CONFIGURATION AND PROTECTION MOTOROLA USER’S MANUAL...
Page 227: System Configuration Registers
* The reset value is a reset configuration word value, extracted from the indicated internal data bus lines. WARNING Software must not change any SIUMCR fields controlled by the reset configuration word while the functions that these fields control are ac- tive. MPC555 MPC556 SYSTEM CONFIGURATION AND PROTECTION MOTOROLA USER’S MANUAL Rev.
Page 228 1 = IRQ[2]/CR/SGPIOC[2]/MTS functions as MTS 25:31 — Reserved NOTES: 1. WE/BE is selected per memory region by WEBS in the approprite BR register in the memory controller. MPC555 MPC556 SYSTEM CONFIGURATION AND PROTECTION MOTOROLA USER’S MANUAL Rev. 15 October 2000...
Page 229 ADDR[8:31] 10 (single-chip with address show SPGIOD[0:15] SPGIOD[16:31] ADDR[8:31] cycles for debugging) 11 (single-chip) SPGIOD[0:15] SPGIOD[16:31] SPGIOA[8:31] MPC555 MPC556 SYSTEM CONFIGURATION AND PROTECTION MOTOROLA USER’S MANUAL Rev. 15 October 2000 6-21 For More Information On This Product, Go to: www.freescale.com...
Page 230: Internal Memory Map Register
The internal memory map register (IMMR) is a special register located within the MPC555 / MPC556 special register space. The IMMR contains identification of a spe- cific device as well as the base for the internal memory map. Based on the value read from this register, software can deduce availability and location of any on-chip system resources.
Page 231: External Master Control Register (Emcr)
It would not change if the part is changed to fix a bug in an existing module. The MPC555 / MPC556 chip has an ID of 0x30.
Page 232 1 = Not a reservation Control attribute. CONT drives the internal bus control bit attribute as follows: CONT 0 = Access to MPC555 / MPC556 control register, or control cycle access 1 = Access to global address map — Reserved Trace attribute.
Page 233: Siu Interrupt Registers
IRM0* LVM0 IRM1 LVM1 IRM2 LVM2 IRM3 LVM3 IRM4 LVM4 IRM5 LVM5 IRM6 LVM6 IRM7 LVM7 RESET: MPC555 MPC556 SYSTEM CONFIGURATION AND PROTECTION MOTOROLA USER’S MANUAL Rev. 15 October 2000 6-25 For More Information On This Product, Go to: www.freescale.com...
Page 234: Siu Interrupt Edge Level Register (Siel)
IRQ line will be detected as an interrupt request. The WMx (wake-up mask) bit, if set, indicates that an interrupt request detection in the corresponding line causes the MPC555 / MPC556 to exit low-power mode. SIEL — SIU Interrupt Edge Level Register...
Page 235: System Protection Registers
1 = Software watchdog stops while FREEZE is asserted Software watchdog enable. Software should clear this bit after a system reset to disable the SWT. 0 = Watchdog is disabled 1 = Watchdog is enabled MPC555 MPC556 SYSTEM CONFIGURATION AND PROTECTION MOTOROLA USER’S MANUAL Rev.
Page 236: Software Service Register (Swsr)
The SWSR is the location to which the SWT servicing sequence is written. To prevent SWT time-out, the user should write a 0x556C followed by 0xAA39 to this register. The SWSR can be written at any time but returns all zeros when read. MPC555 MPC556 SYSTEM CONFIGURATION AND PROTECTION MOTOROLA USER’S MANUAL...
Page 237: Transfer Error Status Register (Tesr)
TESR — Transfer Error Status Register 0x2F C020 RESERVED RESET: RESERVED IEXT IBMT RESERVED DEXT RESERVED RESET: MPC555 MPC556 SYSTEM CONFIGURATION AND PROTECTION MOTOROLA USER’S MANUAL Rev. 15 October 2000 6-29 For More Information On This Product, Go to: www.freescale.com...
Page 238: System Timer Registers
6.13.4.1 Decrementer Register The 32-bit decrementer register is defined by the MPC555 / MPC556 architecture. The values stored in this register are used by a down counter to cause decrementer excep- tions. The decrementer causes an exception whenever bit zero changes from a logic zero to a logic one.
Page 239: Time Base Reference Registers
The reg- ister can be read anytime. A status bit is cleared by writing a one to it. (Writing a zero has no effect.) More than one bit can be cleared at a time. MPC555 MPC556 SYSTEM CONFIGURATION AND PROTECTION MOTOROLA USER’S MANUAL...
Page 240: Real-Time Clock Status And Control Register
Registers Lock Mechanism. RTCSC — Real-Time Clock Status and Control Register 0x2F C220 RTCIRQ served RESET: — — MPC555 MPC556 SYSTEM CONFIGURATION AND PROTECTION MOTOROLA USER’S MANUAL Rev. 15 October 2000 6-32 For More Information On This Product, Go to: www.freescale.com...
Page 241: Real-Time Clock Register (Rtc)
See 8.9.3.2 Keep Alive Power Registers Lock Mecha- nism. RTCAL — Real-Time Clock Alarm Register 0x2F C22C ALARM RESET: UNCHANGED MPC555 MPC556 SYSTEM CONFIGURATION AND PROTECTION MOTOROLA USER’S MANUAL Rev. 15 October 2000 6-33 For More Information On This Product,...
Page 242: Periodic Interrupt Status And Control Register (Piscr)
The PITC register contains the 16 bits to be loaded in a modulus counter. This register is readable and writable at any time. PITC — Periodic Interrupt Timer Count 0x2F C244 PITC RESET: RESERVED RESET: MPC555 MPC556 SYSTEM CONFIGURATION AND PROTECTION MOTOROLA USER’S MANUAL Rev. 15 October 2000 6-34 For More Information On This Product,...
Page 243: Periodic Interrupt Timer Register (Pitr)
Periodic interrupt timing count — This field contains the current count remaining for the periodic 0:15 timer. Writes have no effect on this field. 16:31 — Reserved MPC555 MPC556 SYSTEM CONFIGURATION AND PROTECTION MOTOROLA USER’S MANUAL Rev. 15 October 2000...
Page 244: General-Purpose I/O Registers
6.13.5.2 SGPIO Data Register 2 (SGPIODT2) SGPIODT2 — SGPIO Data Register 2 0x2F C028 SGPIOC[0:7] SGPIOA[8:15] RESET: SGPIOA[16:23] SGPIOA[24:31] RESET: MPC555 MPC556 SYSTEM CONFIGURATION AND PROTECTION MOTOROLA USER’S MANUAL Rev. 15 October 2000 6-36 For More Information On This Product, Go to: www.freescale.com...
Page 245: Sgpio Control Register (Sgpiocr)
— Reserved SDDRD SGPIO data direction for SGPIOD[24:31]. Each SDDRD bit 24:31 controls the direction of 24:31 [24:31] the corresponding SGPIOD pin [24:31]. MPC555 MPC556 SYSTEM CONFIGURATION AND PROTECTION MOTOROLA USER’S MANUAL Rev. 15 October 2000 6-37 For More Information On This Product,...
Page 246 Table 6-24 describes the bit values for data direction control. Table 6-24 Data Direction Control SDDR/GDDR Operation SGPIO configured as input SGPIO configured as output MPC555 MPC556 SYSTEM CONFIGURATION AND PROTECTION MOTOROLA USER’S MANUAL Rev. 15 October 2000 6-38 For More Information On This Product,...
Page 247: Reset Operation
This section describes the MPC555 / MPC556 reset sources, operation, control, and status. 7.1 Reset Operation The MPC555 / MPC556 has several inputs to the reset logic which include the follow- ing: • Power on reset • External hard reset pin (HRESET) •...
Page 248: Hard Reset
Freescale Semiconductor, Inc. If the MPC555 / MPC556 is in single-chip mode and limp mode is enabled, the internal PLL is not required to be locked before the chip exits power-on reset. After exiting the power-on reset state, the MCU continues to drive the HRESET and SRESET pins for 512 system clock cycles.
Page 249: Loss Of Lock
MPC555 / MPC556 input clock. Erroneous opera- tion could also occur if devices with a PLL use the MPC555 / MPC556 CLKOUT signal. This source of reset can be optionally asserted if the LOLRE bit in the PLL, low-power, and reset control register (PLPRCR) is set.
Page 250: Data Coherency During Reset
JTAG Reset 7.3 Data Coherency During Reset The MPC555 / MPC556 supports data coherency and avoids data corruption while re- set. If a cycle is to be executed when detecting any SRESET or HRESET source, then the cycle will either complete or will not start before generating the corresponding reset control signal.
Page 251: Reset Status Register
0 = No JTAG reset has occurred 1 = A JTAG reset has occurred On-chip clock switch OCCS 0 = No on-chip clock switch reset has occurred 1 = An on-chip clock switch reset has occurred MPC555 MPC556 RESET MOTOROLA USER’S MANUAL Rev. 15 October 2000 For More Information On This Product, Go to: www.freescale.com...
Page 252: Reset Configuration
Table 7-3 Reset Status Register Bit Descriptions (Continued) Bit(s) Name Description Illegal bit change. This bit is set when the MPC555 / MPC556 changes any of the following bits when they are locked: ILBC LPM[0:1], locked by the LPML bit...
Page 253: Reset Configuration Basic Scheme
If the PRDS control bit in the PDMCR register is set and HRESET and RSTCONF are asserted, the MPC555 / MPC556 pulls the data bus low with a weak resistor. The user can overwrite this default by driving the appropriate bit high. See...
Page 254: Reset Configuration Sampling Scheme For "Short" Poreset Assertion, Limp Mode Disabled
HRESET RSTCONF Tsup Internal DATA[0:31] Default RSTCONF Controlled Figure 7-2 Reset Configuration Sampling Scheme For “Short” PORESET Assertion, Limp Mode Disabled MPC555 MPC556 RESET MOTOROLA USER’S MANUAL Rev. 15 October 2000 For More Information On This Product, Go to: www.freescale.com...
Page 255: Reset Configuration Timing For Short" Poreset Assertion, Limp Mode Enabled
“Short” PORESET Assertion, Limp Mode Enabled CLKOUT PLL lock PORESET Internal PORESET HRESET RSTCONF Tsup Internal DATA[0:31] Default RSTCONF Controlled Figure 7-4 Reset Configuration Timing for MPC555 MPC556 RESET MOTOROLA USER’S MANUAL Rev. 15 October 2000 For More Information On This Product, Go to: www.freescale.com...
Page 256 Freescale Semiconductor, Inc. “Long” PORESET Assertion, Limp Mode Disabled MPC555 MPC556 RESET MOTOROLA USER’S MANUAL Rev. 15 October 2000 7-10 For More Information On This Product, Go to: www.freescale.com...
Page 257: Reset Configuration Sampling Timing Requirements
Freescale Semiconductor, Inc. Figure 7-5 Reset Configuration Sampling Timing Requirements MPC555 MPC556 RESET MOTOROLA USER’S MANUAL Rev. 15 October 2000 7-11 For More Information On This Product, Go to: www.freescale.com...
Page 258: Hard Reset Configuration Word
Debug pins configuration. See 6.13.1.1 SIU Module Configuration Register for this field 9:10 DBGC definition. The default value is for these pins to function as VFLS[0:1], BI, BR, BG, and BB. MPC555 MPC556 RESET MOTOROLA USER’S MANUAL Rev. 15 October 2000...
Page 259: Soft Reset Configuration
Exception Compression — This bit determines the operation of the MPC555 with exceptions. EXC_ If this bit is set, than the MPC555 assumes that ALL the exception routines are in compressed COMP code. The default indicates the exceptions are all non-compressed. See Table 4-8.
Page 260 Freescale Semiconductor, Inc. MPC555 MPC556 RESET MOTOROLA USER’S MANUAL Rev. 15 October 2000 7-14 For More Information On This Product, Go to: www.freescale.com...
Page 261: Overview
(PLPRCR), and the PLL. All of the MPC555 peripherals on the IMB bus derive its clock timing from the UIMB module. The UIMB runs on the main system clock, but can divide the system frequen- cy in half.
Page 262: Clock Unit Block Diagram
RTC / PIT Clock and DRIVER XTAL Main Clock /4 or /256 Oscillator EXTAL Figure 8-1 Clock Unit Block Diagram MPC555 MPC556 CLOCKS AND POWER CONTROL MOTOROLA USER’S MANUAL Rev. 15 October 2000 For More Information On This Product, Go to: www.freescale.com...
Page 263: System Clock Sources
The PLL can perform the following functions: • Frequency multiplication MPC555 MPC556 CLOCKS AND POWER CONTROL MOTOROLA USER’S MANUAL Rev.
Page 264: Frequency Multiplication
When operating with the backup clock, the system clock (and CLK- OUT) is one-half of the ring oscillator frequency. (i.e., the system clock is a nominal seven MHz). The time base and PIT clocks will be twice the system clock frequency. MPC555 MPC556 CLOCKS AND POWER CONTROL MOTOROLA USER’S MANUAL...
Page 265: Pll Pins
• XFC — External filter capacitor. XFC connects to the off-chip capacitor for the PLL filter. One terminal of the capacitor is connected to XFC, and the other termi- nal is connected to VDDSYN. The off-chip capacitor must have the following values: MPC555 MPC556 CLOCKS AND POWER CONTROL MOTOROLA USER’S MANUAL...
Page 266: System Clock During Pll Loss Of Lock
This block generates all other clocks in normal operation, but has the ability to divide the output frequency of the VCO before it gen- erates the general system clocks sent to the rest of the MPC555 / MPC556. The PLL System Frequency (FREQ ) is always divided by at least 2.
Page 267: Mpc555 / Mpc556 Internal Clock Signals
RTDIV and RTSEL bits in the SCCR. When the backup clock is functioning as the system clock, the backup clock is automatically selected as the time base clock source and is twice the MPC555 / MPC556 system clock. GCLK1...
Page 268 Figure 8-7. GCLK1_50 rises simultaneously with GCLK1. When the MPC555 / MPC556 is not in gear mode, the falling edge of GCLK1_50 occurs in the middle of the high phase of GCLK2_50. EBDF determines the division factor between GCLK1/GCLK2 and GCLK1_50/GCLK2_50.
Page 269: General System Clocks
GCLK2_50) are the basic clock supplied to all modules and sub-modules on the MPC555 / MPC556. GCLK1C and GCLK2C are supplied to the RCPU and to the BBC. GCLK1C and GCLK2C are stopped when the chip enters the doze-low power mode.
Page 270: General System Clocks Select
Abrupt changes in the divide ratio can cause linear changes in the operating currents of the MPC555 / MPC556. Insure that the proper power supply filtering is available to handle this change instantaneously.
Page 271: Timing Diagram
FREQ DFNH DFNL EBDF )or 2 Figure 8-7 shows the timing of USIU clocks when DFNH = 1 or DFNL = 0. MPC555 MPC556 CLOCKS AND POWER CONTROL MOTOROLA USER’S MANUAL Rev. 15 October 2000 8-11 For More Information On This Product,...
Page 272: Clkout
(remaining in the high state). The drive strength is controlled by the EE- CLK[0:1] bits in the SCCR. Disabling ENGCLK can reduce power consumption, noise, and electromagnetic interference on the printed circuit board. Mask sets prior to K62N default to VCO/4. MPC555 MPC556 CLOCKS AND POWER CONTROL MOTOROLA USER’S MANUAL...
Page 273: Clock Source Switching
Figure 8-8 describes the clock switching control logic. Table 8-3 summarizes the sta- tus and control for each state. MPC555 MPC556 CLOCKS AND POWER CONTROL MOTOROLA USER’S MANUAL Rev. 15 October 2000...
Page 274: Clock Source Flow Chart
HRESET to switch the system clock to BUCLK or PLL. At PORESET negation, if the PLL is not locked, the loss-of-clock sticky bit (LOCSS) is asserted, and the chip should operate with BU- CLK. MPC555 MPC556 CLOCKS AND POWER CONTROL MOTOROLA USER’S MANUAL...
Page 275: Low-Power Modes
The user cannot change the LPM or CSRC bits when the MCU is in doze mode. Table 8-6 summarizes the control bit descriptions for the different clock power modes. MPC555 MPC556 CLOCKS AND POWER CONTROL MOTOROLA USER’S MANUAL...
Page 276: Power Mode Descriptions
• RTC, PIT, or time base interrupts (if enabled) • Decrementer exception The system response to asynchronous interrupts is fast. The wake-up time from nor- mal-low, doze-high, doze-low, and sleep mode due to an asynchronous interrupt or MPC555 MPC556 CLOCKS AND POWER CONTROL MOTOROLA USER’S MANUAL...
Page 277: Exiting From Normal-Low Mode
The system changes from doze mode to normal-high mode whenever an interrupt is pending from the interrupt controller. 8.8.3.3 Exiting from Deep-Sleep Mode The system switches from deep-sleep mode to normal-high mode if any of the follow- ing conditions is met: MPC555 MPC556 CLOCKS AND POWER CONTROL MOTOROLA USER’S MANUAL Rev.
Page 278: Exiting From Power-Down Mode
Refer to 8.9.3 Keep Alive Power for more information. 8.8.3.5 Low-Power Modes Flow Figure 8-9 shows the flow among the different power modes. MPC555 MPC556 CLOCKS AND POWER CONTROL MOTOROLA USER’S MANUAL Rev. 15 October 2000 8-18 For More Information On This Product, Go to: www.freescale.com...
Page 279: Mpc555 / Mpc556 Low-Power Modes Flow Diagram
TEXPS receives the zero value by writing one. Writing of zero has no effect on TEXPS. The switch from normal-high to normal-low is enable only if the conditions to asynchronous interrupt are cleared Figure 8-9 MPC555 / MPC556 Low-Power Modes Flow Diagram MPC555 MPC556...
Page 280: Basic Power Structure
• VPP VDDL – 0.3 V, but VPP – VDDL < 4.0 volts 8.9.2 Chip Power Structure The MPC555 / MPC556 provides a wide range of possibilities for power supply con- nections. Figure 8-10 illustrates the different power supply sources for each of the ba- sic units on the chip.
Page 281: Vddsyn, Vsssyn
8.9.2.9 VDDSRAM VDDSRAM supplies power to the 26-Kbyte SRAM module and the DPTRAM. It can be used to keep the contents on the SRAM stable while the rest of the MPC555 / MPC556 is powered down for standby operation. 8.9.2.10 VSS VSS provides the ground reference for the MPC555 / MPC556.
Page 282: Keep Alive Power
Figure 8-11 illustrates an example of a switching scheme for an optimized low-power system. SW1 and SW2 can be unified in only one switch if VDDSYN and VDDI/VDDL are supplied by the same source. MPC555 MPC556 CLOCKS AND POWER CONTROL MOTOROLA USER’S MANUAL...
Page 283: Keep Alive Power Registers Lock Mechanism
Supply Figure 8-11 External Power Supply Scheme The MPC555 / MPC556 asserts the TEXP signal, if enabled, when the RTC or TB time value matches the value programmed in the associated alarm register or when the PIT or DEC value reaches zero. The TEXP signal is negated when the TEXPS status bit is written to one.
Page 284 Reset Status Register (RSR) 0x2F C288 0x2F C388 Reset Status Register Key (RSRK) Table 7-3 for bit descriptions. MPC555 MPC556 CLOCKS AND POWER CONTROL MOTOROLA USER’S MANUAL Rev. 15 October 2000 8-24 For More Information On This Product,...
Page 285: Vddsram Supply Failure Detection
8.11 Power Up/Down Sequencing Figure 8-13 Figure 8-14 detail the power-up sequencing for MPC555 / MPC556 during normal operation. Note that for each of the conditions detailing the voltage re- lationships the absolute bounds of the minimum and maximum voltage supply cannot be violated, i.e.
Page 286: No Standby, No Kapwr, All System Power On/Off
0.74 V for the 3-V supply and greater than 0.8 V for the 5-V supply, then the circuitry inside the MPC555 / MPC556 will act as a load to the respective supply and will dis- charge the supply line down to these values. Since the 3-V logic represents a larger load to the supply chip, the 3-V supply line will decay faster than the 5-V supply line.
Page 287 Normal system power is defined as VDDL = VDDI = VDDF = VDDSYN = VPP = VDDSRAM = KAPWR = 3.3 ± 0.3 V and VDDA = VDDH = 5.0 ± 0.5 V MPC555 MPC556 CLOCKS AND POWER CONTROL MOTOROLA USER’S MANUAL...
Page 288: Clocks Unit Programming Model
4. EQ3 = (MODCK1 & MODCK2 & MODCK3) | (MODCK1 & MODCK2 & MODCK3) | (MODCK1 & MODCK2 & MODCK3). See Table 8-1. 5. On mask sets prior to K62N, ENGDIV defaults to 0b000001. MPC555 MPC556 CLOCKS AND POWER CONTROL MOTOROLA USER’S MANUAL Rev.
Page 289 LME is cleared. 0 = Do not switch to the backup clock ring oscillator 1 = Switch to backup clock ring oscillator — Reserved MPC555 MPC556 CLOCKS AND POWER CONTROL MOTOROLA USER’S MANUAL Rev. 15 October 2000...
Page 290 ENGCLK is not guaranteed. NOTE: The default (Power On Reset) value of ENGDIV will be 0b111111 on all mask sets after K62N. The default for previous mask sets (J76N, K02A, and K83H) is 0b000001. MPC555 MPC556 CLOCKS AND POWER CONTROL MOTOROLA USER’S MANUAL...
Page 291: Pll, Low-Power, And Reset-Control Register (Plprcr)
110 = Divide by 64 111 = Reserved 8.12.2 PLL, Low-Power, and Reset-Control Register (PLPRCR) The PLL, low-power, and reset-control register (PLPRCR) is a 32-bit register powered by the keep alive power supply. MPC555 MPC556 CLOCKS AND POWER CONTROL MOTOROLA USER’S MANUAL Rev.
Page 292 PLL lock condition is not met when HRESET is asserted, and cleared if the PLL is locked when HRESET is asserted. 0 = No loss of oscillator has been detected 1 = Loss of oscillator has been detected MPC555 MPC556 CLOCKS AND POWER CONTROL MOTOROLA USER’S MANUAL...
Page 293 1 = Loss of lock causes HRESET assertion LOLRE Note: if limp mode is enabled, use the COLIR feature instead of setting the LOLRE bit. See 8.12.3 Change of Lock Interrupt Register (COLIR). MPC555 MPC556 CLOCKS AND POWER CONTROL MOTOROLA USER’S MANUAL Rev.
Page 294: Change Of Lock Interrupt Register (Colir)
A status bit is cleared by writing a one (writing a zero does not affect a status bit’s value). The COLIR is memory mapped into the MPC555 / MPC556 USIU register map. COLIR — Change of Lock Interrupt Register...
Page 295 VDDSRAM detector disable. VSRDE 0 = VDDSRAM detection circuit is enabled 1 = VDDSRAM detection circuit is disabled 6:15 — Reserved MPC555 MPC556 CLOCKS AND POWER CONTROL MOTOROLA USER’S MANUAL Rev. 15 October 2000 8-35 For More Information On This Product,...
Page 296 Freescale Semiconductor, Inc. MPC555 MPC556 CLOCKS AND POWER CONTROL MOTOROLA USER’S MANUAL Rev. 15 October 2000 8-36 For More Information On This Product, Go to: www.freescale.com...
Page 297: Features
• Easy to interface to slave devices • Bus is synchronous (all signals are referenced to rising edge of bus clock) • Bus can operate at the same frequency as the MPC555 / MPC556 or half the fre- quency. 9.2 Bus Transfer Signals The bus transfers information between the MPC555 / MPC556 and external memory of a peripheral device.
Page 298: Bus Control Signals
Bus cycles can be completed in two clock cycles. For all inputs, the MPC555 / MPC556 latches the level of the input during a sample window around the rising edge of the clock signal. This window is illustrated in Figure 9-1, where tsu and tho are the input setup and hold times, respectively.
Page 299: Bus Interface Signal Descriptions
RETRY BI (STS) Transfer Cycle Termination Arbitration Figure 9-2 MPC555 / MPC556 Bus Signals 9.4 Bus Interface Signal Descriptions Table 9-1 diatribes each signal in the bus interface unit. More detailed descriptions can be found in subsequent subsections. MPC555 MPC556...
Page 300 Driven low indicates that a burst transfer is in progress. Driven high indicates that the current trans- fer is not a burst. The MPC555 / MPC556 does not support burst accesses to internal slaves. Driven by the MPC555 / MPC556 along with the ad- dress when it owns the external bus.
Page 301 Pins Active Description In the case of regular transaction, this signal is driven by the slave device to indicate that the MPC555 / MPC556 must relinquish the ownership of the bus and retry the cycle. RETRY When an external master owns the bus and the inter-...
Page 302 DATA[8:15] DATA[16:23] 2 DATA[24:31] 3 Driven by the MPC555 / MPC556 when it owns the external bus and it initiated a write transaction to a slave device. For single beat transactions, the byte lanes not selected for the transfer by ADDR[30:31] DATA[0:31] and TSIZ[0:1] do not supply valid data.
Page 303: Bus Operations
CPU circuitry (including the bus interface) which is phase-locked to the CLKOUT out- put signal. All signals for the MPC555 / MPC556 bus interface are specified with respect to the rising edge of the external CLKOUT and are guaranteed to be sampled as inputs or changed as outputs with respect to that edge.
Page 304: Basic Transfer Protocol
9.5.1 Basic Transfer Protocol The basic transfer protocol defines the sequence of actions that must occur on the MPC555 / MPC556 bus to perform a complete bus transaction. A simplified scheme of the basic transfer protocol is illustrated in Figure 9-3.
Page 305: Basic Flow Diagram Of A Single Beat Read Cycle
Drive address and attributes Receive address Return data Assert transfer acknowledge (TA) Receive data Figure 9-4 Basic Flow Diagram of a Single Beat Read Cycle MPC555 MPC556 EXTERNAL BUS INTERFACE MOTOROLA USER’S MANUAL Rev. 15 October 2000 For More Information On This Product,...
Page 306: Single Beat Read Cycle–Basic Timing–Zero Wait States
Assert BB, drive address and assert TS ADDR[0:31] RD/WR TSIZ[0:1] BURST, BDIP Data Data is valid Figure 9-5 Single Beat Read Cycle–Basic Timing–Zero Wait States MPC555 MPC556 EXTERNAL BUS INTERFACE MOTOROLA USER’S MANUAL Rev. 15 October 2000 9-10 For More Information On This Product,...
Page 307: Single Beat Write Flow
The basic write cycle begins with a bus arbitration, followed by the address transfer, then the data transfer. The handshakes are illustrated in the following flow and timing diagrams as applicable to the fixed transaction protocol. MPC555 MPC556 EXTERNAL BUS INTERFACE MOTOROLA USER’S MANUAL...
Page 308: Basic Flow Diagram Of A Single Beat Write Cycle
Assert transfer start (TS) Drive address and attributes Drive data Assert transfer acknowledge (TA) Interrupt data driving Figure 9-7 Basic Flow Diagram of a Single Beat Write Cycle MPC555 MPC556 EXTERNAL BUS INTERFACE MOTOROLA USER’S MANUAL Rev. 15 October 2000...
Page 309: Single Beat Basic Write Cycle Timing, Zero Wait States
Assert BB, drive address and assert TS ADDR[0:31] RD/WR TSIZ[0:1] BURST, BDIP Data Data is sampled Figure 9-8 Single Beat Basic Write Cycle Timing, Zero Wait States MPC555 MPC556 EXTERNAL BUS INTERFACE MOTOROLA USER’S MANUAL Rev. 15 October 2000 9-13 For More Information On This Product,...
Page 310: Single Beat Flow With Small Port Size
In this case, the MPC555 / MPC556 attempts to initiate a transfer as in the normal case. If the bus interface receives a small port size (16 or 8 bits) indication before the transfer acknowledge to the first beat (through the internal memory controller), the MCU initiates successive transactions until the completion of the data transfer.
Page 311: Burst Transfer
16 bytes (four words). A non-wrapping burst access stops accessing the external device when the word address is modulo four. The MPC555 / MPC556 begins the ac- cess by supplying a starting address that points to one of the words and requiring the memory device to sequentially drive or sample each word on the data bus.
Page 312: Burst Mechanism
In this case, the MPC555 / MPC556 attempts to initiate a burst transfer as in the normal case. If the memory controller signals to the bus interface that the external device has a small port size (8 or 16 bits), and if the burst is accepted, the bus interface completes a burst of 8 or 16 beats.
Page 313 MEMORY CONTROLLER for more information. In the MPC555 / MPC556, no internal master initiates write bursts. The MPC555 / MPC556 is designed to perform this kind of transaction in order to support an external master that is using the memory controller services. Refer to 10.7 Memory Controller...
Page 314: Basic Flow Diagram Of A Burst Read Cycle
Negate Burst Data in Progress (BDIP) Assert Transfer Acknowledge (TA) Drive Last Data BDIP Asserted & Assert TA Receive Sata Figure 9-11 Basic Flow Diagram Of A Burst Read Cycle MPC555 MPC556 EXTERNAL BUS INTERFACE MOTOROLA USER’S MANUAL Rev. 15 October 2000 9-18 For More Information On This Product, Go to: www.freescale.com...
Page 315: Burst-Read Cycle–32-Bit Port Size–Zero Wait State
Data Data Data is Valid is Valid is Valid is Valid Figure 9-12 Burst-Read Cycle–32-Bit Port Size–Zero Wait State MPC555 MPC556 EXTERNAL BUS INTERFACE MOTOROLA USER’S MANUAL Rev. 15 October 2000 9-19 For More Information On This Product, Go to: www.freescale.com...
Page 316: Burst-Read Cycle–32-Bit Port Size–One Wait State
Data Data Wait State is Valid is Valid is Valid is Valid Figure 9-13 Burst-Read Cycle–32-Bit Port Size–One Wait State MPC555 MPC556 EXTERNAL BUS INTERFACE MOTOROLA USER’S MANUAL Rev. 15 October 2000 9-20 For More Information On This Product, Go to: www.freescale.com...
Page 317: Burst-Read Cycle–32-Bit Port Size–Wait States Between Beats
Data Data is Valid is Valid is Valid is Valid Wait State Figure 9-14 Burst-Read Cycle–32-Bit Port Size–Wait States Between Beats MPC555 MPC556 EXTERNAL BUS INTERFACE MOTOROLA USER’S MANUAL Rev. 15 October 2000 9-21 For More Information On This Product,...
Page 318: Burst-Read Cycle, 16-Bit Port Size
Freescale Semiconductor, Inc. CLKOUT ADDR[0:31] ADDR[28:31] = 0000 RD/WR TSIZ[0:1] BURST BDIP Data[0:15] Figure 9-15 Burst-Read Cycle, 16-Bit Port Size MPC555 MPC556 EXTERNAL BUS INTERFACE MOTOROLA USER’S MANUAL Rev. 15 October 2000 9-22 For More Information On This Product, Go to: www.freescale.com...
Page 319: Basic Flow Diagram Of A Burst Write Cycle
Receive Bus Grant (BG) from Arbiter Assert Bus Busy (BB) if No Other Master is Driving Assert Transfer Start (TS) Drive Address and Attributes Drive BURST Asserted MTS Asserted (from MPC555) Drive data Receive Address ADDR[28:29] mod 4 = ? Assert BDIP...
Page 320: Burst-Write Cycle, 32-Bit Port Size, Zero Wait States
Data Data Data Data Data is Sampled is Sampled is Sampled is Sampled Figure 9-17 Burst-Write Cycle, 32-Bit Port Size, Zero Wait States MPC555 MPC556 EXTERNAL BUS INTERFACE MOTOROLA USER’S MANUAL Rev. 15 October 2000 9-24 For More Information On This Product,...
Page 321: Burst-Inhibit Cycle, 32-Bit Port Size (Emulated Burst)
* BURST and BDIP will be asserted for one cycle if the RCPU core requests a burst, but the USIU splits it into a sequence of normal cycles. Figure 9-18 Burst-Inhibit Cycle, 32-Bit Port Size (Emulated Burst) MPC555 MPC556 EXTERNAL BUS INTERFACE MOTOROLA USER’S MANUAL...
Page 322: Non-Wrap Burst With Three Beats
(n modulo 4 = 1) ADDR[30:31] RD/WR TSIZ[0:1] BURST Expects Another Data BDIP Data Figure 9-19 Non-Wrap Burst with Three Beats MPC555 MPC556 EXTERNAL BUS INTERFACE MOTOROLA USER’S MANUAL Rev. 15 October 2000 9-26 For More Information On This Product, Go to: www.freescale.com...
Page 323: Non-Wrap Burst With One Data Beat
BURST Is Never Asserted BDIP First and Last Beat Data DATA is Sampled Figure 9-20 Non-Wrap Burst with One Data Beat MPC555 MPC556 EXTERNAL BUS INTERFACE MOTOROLA USER’S MANUAL Rev. 15 October 2000 9-27 For More Information On This Product,...
Page 324: Alignment And Packaging Of Transfers
• Word accesses require address bits 30 – 31 to equal zero • Burst accesses require address bits 30 – 31 to equal zero The MPC555 / MPC556 performs operand transfers through its 32-bit data port. If the transfer is controlled by the internal memory controller, the MPC555 / MPC556 can support 8- and 16-bit data port sizes.
Page 325: Interface To Different Port Size Devices
32-bit Port Size 16-bit Port Size 8-bit Port Size Figure 9-22 Interface To Different Port Size Devices Table 9-2 lists the bytes required on the data bus for read cycles. MPC555 MPC556 EXTERNAL BUS INTERFACE MOTOROLA USER’S MANUAL Rev. 15 October 2000...
Page 326: Arbitration Phase
The external bus design provides for a single bus master at any one time, either the MPC555 / MPC556 or an external device. One or more of the external devices on the bus can have the capability of becoming bus master for the external bus. Bus arbitra- tion may be handled either by an external central bus arbiter or by the internal on-chip arbiter.
Page 327: Bus Request
The MPC555 / MPC556, however, guarantees data coherency for access to a small port size and for decomposed bursts. This means that the MPC555 / MPC556 will not release the bus before the completion of the transactions that are considered atomic.
Page 328: Bus Grant
BR or kept asserted for the current master to park the bus. When configured for external central arbitration, BG is an input signal to the MPC555 / MPC556 from the external arbiter. When the internal on-chip arbiter is used, this sig- nal is an output from the internal arbiter to the external bus master.
Page 329: Internal Bus Arbiter
The MPC555 / MPC556 can be configured at system reset to use the internal bus ar- biter. In this case, the MPC555 / MPC556 will be parked on the bus. The parking fea- ture allows the MPC555 / MPC556 to skip the bus request phase, and if BB is negated, assert BB and initiate the transaction without waiting for BG from the arbiter.
Page 330 3. Refer to 6.13.1.1 SIU Module Configuration Register. Figure 9-26 illustrates the internal finite-state machine that implements the arbiter pro- tocol. MPC555 MPC556 EXTERNAL BUS INTERFACE MOTOROLA USER’S MANUAL Rev. 15 October 2000 9-34 For More Information On This Product, Go to: www.freescale.com...
Page 331: Address Transfer Phase Signals
Freescale Semiconductor, Inc. External Owner MPC555 / MPC556 Internal Master With Higher = t.s External Master Priority than the External Device Requests Bus Requires the Bus Ext Master Release Bus MPC555 / IDLE MPC556 Wait = t.s = t.s MCU Needs...
Page 332: Transfer Start
BURST is driven by the bus master at the beginning of the bus cycle along with the address to indicate that the transfer is a burst transfer. The MPC555 / MPC556 supports a non-wrapping, four-beat maximum, critical word first burst type. The maximum burst size is 16 bytes. For a 32-bit port, the burst in- cludes four beats.
Page 333: Transfer Size
Function 0 = Special transfer 1 = Normal transfer 0 = Start of transfer 1 = No transfer Must equal zero on MPC555 / MPC556 0 = Supervisor mode 1 = User mode 0 = Instruction 1 = Data Reservation/Program Trace...
Page 334: Burst Data In Progress
• Transfer error acknowledge (TEA) 9.5.8.1 Transfer Acknowledge Transfer acknowledge indicates normal completion of the bus transfer. During a burst cycle, the slave asserts this signal with every data beat returned or accepted. MPC555 MPC556 EXTERNAL BUS INTERFACE MOTOROLA USER’S MANUAL Rev.
Page 335: Burst Inhibit
Figure 9-27 Figure 9-28. Slave 1 External Bus Acknowledge Signals Slave 2 Figure 9-27 Termination Signals Protocol Basic Connection MPC555 MPC556 EXTERNAL BUS INTERFACE MOTOROLA USER’S MANUAL Rev. 15 October 2000 9-39 For More Information On This Product, Go to: www.freescale.com...
Page 336: Storage Reservation
Figure 9-28 Termination Signals Protocol Timing Diagram 9.5.9 Storage Reservation The MPC555 / MPC556 storage reservation protocol supports a multi-level bus struc- ture. For each local bus, storage reservation is handled by the local reservation logic. The protocol tries to optimize reservation cancellation such that a PowerPC processor is notified of storage reservation loss on a remote bus only when it has issued a stwcx cycle to that address.
Page 337: Reservation On Local Bus
CLKOUT Figure 9-29 Reservation On Local Bus The MPC555 / MPC556 samples the CR line at the rising edge of CLKOUT. When this signal is asserted, the reservation flag is reset. The EBI samples the logical value of the reservation flag prior to externally starting a bus cycle initiated by the RCPU stwcx instruction.
Page 338: Reservation On Multilevel Bus Hierarchy
The flag is reset when an alternative master on the remote bus accesses the same location in a write cycle. If the MPC555 / MPC556 begins a memory cycle to the previously reserved address (located in the remote bus) as a result of an stwcx in- struction, the following two cases can occur: •...
Page 339: Bus Exception Control Cycles
In the next clock cycle, a normal arbitration procedure occurs again. As shown in the figure, the external master did not use the bus, so the MPC555 / MPC556 initiates a new transfer with the same address and attributes as before.
Page 340: Retry Transfer Timing–Internal Arbiter
Master to Gain the Bus ADDR[0:31] ADDR ADDR RD/WR TSIZ[0:1] BURST Data RETRY (input) Figure 9-31 Retry Transfer Timing–Internal Arbiter MPC555 MPC556 EXTERNAL BUS INTERFACE MOTOROLA USER’S MANUAL Rev. 15 October 2000 9-44 For More Information On This Product, Go to: www.freescale.com...
Page 341: Retry Transfer Timing–External Arbiter
RETRY (input) Figure 9-32 Retry Transfer Timing–External Arbiter When the MPC555 / MPC556 initiates a burst access, the bus interface recognizes the RETRY assertion as a retry termination only if it detects it before the first data beat was acknowledged by the slave device. When the RETRY signal is asserted as a termina-...
Page 342: Retry On Burst Cycle
16-byte transfer recognizes the RETRY signal assertion as a transfer er- ror acknowledge. In the case in which a small port size causes the MPC555 / MPC556 to break a bus transaction into several small transactions, terminating any transaction with RETRY...
Page 343: Termination Signals Protocol Summary
6.2 External Master Modes). In an external master mode, the external master owns the bus, and the direc- tion of most of the bus signals is inverted, relative to its direction when the MPC555 / MPC556 owns the bus. The external master gets ownership of the bus and asserts TS in order to initiate an external master access.
Page 344: Basic Flow Of An External Master Read Access
Freescale Semiconductor, Inc. MPC555 / External Master MPC556 Request Bus (BR) Receives Bus Grant (BG) From Arbiter Asserts Bus Busy (BB) if No Other Master is Driving Assert Transfer Start (TS) Drives Address and Attributes Receives Address Address in Internal...
Page 345: Basic Flow Of An External Master Write Access
Figure 9-35 Basic Flow of an External Master Write Access ,Figure 9-36, Figure 9-37 Figure 9-38 describe read and write cycles from an ex- ternal master accessing internal space in the MPC555 / MPC556. Note that the mini- MPC555 MPC556 EXTERNAL BUS INTERFACE MOTOROLA USER’S MANUAL Rev.
Page 346: Peripheral Mode: External Master Reads From Mpc555 / Mpc556 — Two Wait States
BDIP TS (input) Data TA (output) Minimum 2 Wait States DATA is valid Figure 9-36 Peripheral Mode: External Master Reads from MPC555 / MPC556 — Two Wait States MPC555 MPC556 EXTERNAL BUS INTERFACE MOTOROLA USER’S MANUAL Rev. 15 October 2000...
Page 347 BURST BDIP TS (input) Data TA (output) Minimum 2 Wait States DATA is sampled Figure 9-37 Peripheral Mode: External Master Writes to MPC555 / MPC556; Two Wait States MPC555 MPC556 EXTERNAL BUS INTERFACE MOTOROLA USER’S MANUAL Rev. 15 October 2000...
Page 348: Contention Resolution On External Bus
Freescale Semiconductor, Inc. 9.5.12 Contention Resolution on External Bus When the MPC555 / MPC556 is in slave mode, external master access to the MPC555 / MPC556 internal bus can be terminated with relinquish and retry in order to allow a pending internal-to-external access to be executed.
Page 349: Flow Of Retry Of External Master Read Access
Freescale Semiconductor, Inc. External Master MPC555 / MPC556 Request Bus (BR) Receives BusGrant (BG) from Arbiter Asserts Bus Busy (BB) if No Other Master is Driving Assert Transfer Start (TS) Drives Address and Attributes Assert Retry Release Bus Request (BR) for One Clock and Request Bus (BR) Again...
Page 350: Show Cycle Transactions
(This is different from normal bus read and write accesses.) The address and data of the show cycle must each be valid on the bus for one clock. The data phase must not require a transfer ac- MPC555 MPC556 EXTERNAL BUS INTERFACE MOTOROLA USER’S MANUAL...
Page 351: Instruction Show Cycle Transaction
RD/WR TSIZ[0:1] BURST Data (three-state) Instruction Show Cycle Bus Transaction “Normal” Non-Show Cycle Bus Transaction Figure 9-40 Instruction Show Cycle Transaction MPC555 MPC556 EXTERNAL BUS INTERFACE MOTOROLA USER’S MANUAL Rev. 15 October 2000 9-55 For More Information On This Product,...
Page 352: Data Show Cycle Transaction
BURST Data DATA1 DATA2 Read Data Show Cycle Bus Transaction Write Data Show Cycle Bus Transaction Figure 9-41 Data Show Cycle Transaction MPC555 MPC556 EXTERNAL BUS INTERFACE MOTOROLA USER’S MANUAL Rev. 15 October 2000 9-56 For More Information On This Product,...
Page 353: Overview
The memory controller provides a glueless interface to EPROM, static RAM (SRAM), Flash EPROM (FEPROM), and other peripherals. The general-purpose chip-selects are available on lines CS[0] through CS[3]. CS[0] also functions as the global (boot) MPC555 / MPC556 MEMORY CONTROLLER MOTOROLA USER’S MANUAL...
Page 354: Memory Controller Block Diagram
Freescale Semiconductor, Inc. chip-select for accessing the boot flash EEPROM. The chip select allows zero to 30 wait states. Figure 10-2 is a block diagram of the MPC555 / MPC556 memory controller. INTERNAL ADDRESSES [0:16, AT[0:2] Option Base Register Register...
Page 355: Memory Controller Architecture
(MTS) strobe permits one master on a bus to access external memory through the chip selects on another. The memory controller functionality allows MPC555 / MPC556-based systems to be built with little or no glue logic. A minimal system using no glue logic is shown in Figure 10-3.
Page 356: Associated Registers
Defined 16-bit ports, when connected to data bus lines zero to 15, can be accessed as odd bytes, even bytes, or even half-words. Defined 32- bit ports can be accessed as odd bytes, even bytes, odd half-words, even half-words, MPC555 MPC556 MEMORY CONTROLLER MOTOROLA USER’S MANUAL...
Page 357: Write-Protect Configuration
BDIP signal: normal and late. Note that the BDIP pin itself is con- trolled by the external bus interface logic. Refer to Figure 9-13 Figure 9-14 SECTION 9 EXTERNAL BUS INTERFACE. MPC555 MPC556 MEMORY CONTROLLER MOTOROLA USER’S MANUAL Rev. 15 October 2000...
Page 358: Chip-Select Timing
Transfer. 10.3 Chip-Select Timing The GPCM allows a glueless and flexible interface between the MPC555 / MPC556 and SRAM, EPROM, EEPROM, ROM devices and external peripherals. When an ad- dress and address type matches the values programmed in the BR and OR for one of the memory controller banks, the attributes for the memory cycle are taken from the OR and BR registers as well.
Page 359: Memory Devices Interface Example
10.3.1 Memory Devices Interface Example Figure 10-5 describes the basic connection between the MPC555 / MPC556 and a static memory device. In this case CSx is connected directly to the chip enable (CE) of the memory device. The WE/BE[0:3] lines are connected to the respective W in the memory device where each WE/BE line corresponds to a different data byte.
Page 360: Peripheral Devices Interface Example
10.3.2 Peripheral Devices Interface Example Figure 10-7 illustrates the basic connection between the MPC555 / MPC556 and an external peripheral device. In this case CSx is connected directly to the chip enable (CE) of the memory device and the R/W line is connected to the R/W in the peripheral device.
Page 361: Peripheral Devices Interface
Freescale Semiconductor, Inc. Peripheral MPC555 / MPC556 Address Address RD/WR Data Data Figure 10-7 Peripheral Devices Interface The CSx timing is defined by the setup time required between the address lines and the CE line. The memory controller allows the user to specify the CS timing to meet the setup time required by the peripheral device.
Page 362: Relaxed Timing Examples
— Two clocks for basic cycle — SCY = 1 determines 1 wait state, which is multiplied by two due to TRLX being set. — Extra clock is added due to TRLX effect on the strobes. MPC555 MPC556 MEMORY CONTROLLER MOTOROLA USER’S MANUAL...
Page 363 RD/WR WEBS = ‘0’,Line Acts as BE in Read. WE/BE Data Figure 10-9 Relaxed Timing–Read Access (ACS = 11, SCY = 1, TRLX = 1) MPC555 MPC556 MEMORY CONTROLLER MOTOROLA USER’S MANUAL Rev. 15 October 2000 10-11 For More Information On This Product,...
Page 364 Address ACS = 10 RD/WR WE/BE Data Figure 10-10 Relaxed Timing–Write Access (ACS = 10, SCY = 0, CSNT = 0, TRLX = 1) MPC555 MPC556 MEMORY CONTROLLER MOTOROLA USER’S MANUAL Rev. 15 October 2000 10-12 For More Information On This Product,...
Page 365 ACS!=00 & CSNT = 1 RD/WR WE/BE CSNT = 1 Data Figure 10-11 Relaxed Timing – Write Access (ACS = 11, SCY = 0, CSNT = 1, TRLX = 1) MPC555 MPC556 MEMORY CONTROLLER MOTOROLA USER’S MANUAL Rev. 15 October 2000 10-13 For More Information On This Product, Go to: www.freescale.com...
Page 366: Extended Hold Time On Read Accesses
For devices that require a long disconnection time from the data bus on read access- es, the bit EHTR in the corresponding OR register can be set. In this case any MPC555 / MPC556 access to the external bus following a read access to the referred memory bank is delayed by one clock cycle unless it is a read access to the same bank.
Page 367: Consecutive Accesses (Write After Read, Ehtr = 0)
Because EHTR = 0, no extra clock cycle is inserted between memory cycles. CLOCK Address RD/WR Data Figure 10-13 Consecutive Accesses (Write After Read, EHTR = 0) MPC555 MPC556 MEMORY CONTROLLER MOTOROLA USER’S MANUAL Rev. 15 October 2000 10-15 For More Information On This Product, Go to: www.freescale.com...
Page 368: Consecutive Accesses (Write After Read, Ehtr = 1)
CLOCK Address RD/WR Data Long Tdt allowed Extra clock before next cycle starts. Figure 10-14 Consecutive Accesses (Write After Read, EHTR = 1) MPC555 MPC556 MEMORY CONTROLLER MOTOROLA USER’S MANUAL Rev. 15 October 2000 10-16 For More Information On This Product,...
Page 369 Address RD/WR Data Long Tdt Allowed Extra Clock Before Next Cycle Starts Figure 10-15 Consecutive Accesses (Read After Read From Different Banks, EHTR = 1) MPC555 MPC556 MEMORY CONTROLLER MOTOROLA USER’S MANUAL Rev. 15 October 2000 10-17 For More Information On This Product,...
Page 370: Summary Of Gpcm Timing Options
Data Figure 10-16 Consecutive Accesses (Read After Read From Same Bank, EHTR = 1) 10.3.5 Summary of GPCM Timing Options Table 10-2 summarizes the different combinations of timing options. MPC555 MPC556 MEMORY CONTROLLER MOTOROLA USER’S MANUAL Rev. 15 October 2000...
Page 371 9.5.4 Burst Mechanism. Note that this function can operate only when the cycle termination is internal, using the number of wait states programmed in one of the ORx registers MPC555 MPC556 MEMORY CONTROLLER MOTOROLA USER’S MANUAL Rev. 15 October 2000...
Page 372: Global (Boot) Chip-Select Operation
CSNT ACS[0:1] SCY[0:3] 1111 BSCY[0:2] SETA TRLX NOTE If the MPC555 / MPC556 is configured (in the reset configuration word) to use the internal flash EEPROM as boot memory CS[0] is not asserted. MPC555 MPC556 MEMORY CONTROLLER MOTOROLA USER’S MANUAL Rev.
Page 373: Write And Byte Enable Signals
DMBR), an internal address matches the dual-mapped address range (as pro- grammed in the DMBR), and the cycle type matches AT/ATM field in DMBR/DMOR registers, then the following occur: • The internal flash memory does not respond to that address MPC555 MPC556 MEMORY CONTROLLER MOTOROLA USER’S MANUAL...
Page 374 Where ISB[0:2] represents the bit field in IMMR register that determines the location of the address map of the MPC555 / MPC556. With dual mapping, aliasing of address spaces may occur. This happens when the user maps the dual-mapped region into a region which is also mapped into one of the four regions available in the memory controller.
Page 375: Aliasing Phenomena Illustration
Also, the default state takes the lower two Mbytes of the MPC555 / MPC556 internal flash memory. Hence, caution should be taken to change the dual-mapping setup before the first data ac- cess.
Page 376: Memory Controller External Master Support
CLKOUT during which TS is sampled, until the last TA acknowledges the transfer. Since the external master works synchronously with the MPC555 / MPC556, only setup and hold times around the rising edge of CLK- OUT are important. Once the TS is detected/asserted, the memory controller com- pares the address with each one of its defined valid banks to find a possible match.
Page 377: Synchronous External Master Configuration For Gpcm–Handled Memory Devices
Freescale Semiconductor, Inc. Synchronous External Master BURST BDIP Data ADDR MPC555 / MPC556 Memory Address Address WE/BE BDIP BDIP Data Data BURST BURST Note that the memory controller’s BDIP line is used as a burst_in_progress signal. Figure 10-18 Synchronous External Master Configuration For GPCM–Handled Memory Devices...
Page 378: Synchronous External Master Basic Access (Gpcm Controlled)
Data Figure 10-19 Synchronous External Master Basic Access (GPCM Controlled) Note that since the MPC555 / MPC556 has only 24 address pins, the eight most sig- nificant internal address lines are driven as 0x0000_0000, and so compared in the memory controller’s regions.
Page 379: Programming Model
CS[0]. 10.8.1 General Memory Controller Programming Notes 1. In the case of an external master that accesses an internal MPC555 / MPC556 module (in slave or peripheral mode), if that slave device address also matches one of the memory controller’s regions, the memory controller will not issue any CS for this access, nor will it terminate the cycle.
Page 380: Memory Controller Status Registers (Mstat)
* Reset value is determined by the value on the internal data bus during reset. ** The BR0 Reset value is determined by the value on the internal data bus during reset (reset-configuration word). The reset value of the V bit of BR1-3 = 0. MPC555 MPC556 MEMORY CONTROLLER MOTOROLA USER’S MANUAL...
Page 381 The CS signal does not assert until the V-bit is set. Note that an access to a region that has no V-bit set may cause a bus monitor timeout. Note also that following a system reset, the V-bit in BR0 reflects the value of ID3 in the reset configuration word. MPC555 MPC556 MEMORY CONTROLLER MOTOROLA USER’S MANUAL...
Page 382: Memory Controller Option Registers (Or0 – Or3)
10 = CS is asserted a quarter of a clock after the address lines are valid. 11 = CS is asserted half a clock after the address lines are valid Following a system reset, the ACS bits are reset in OR0. MPC555 MPC556 MEMORY CONTROLLER MOTOROLA USER’S MANUAL...
Page 383: Dual Mapping Base Register (Dmbr)
Name Description Extended hold time on read accesses. This bit, when asserted, inserts an idle clock cycle after a read access from the current bank and any MPC555 / MPC556 write accesses or read accesses EHTR to a different bank.
Page 384: Dual-Mapping Option Register
RESERVED RESET: RESERVED RESET: *It is recommended that this field would hold values that are the power of 2 minus 1 (e.g., - 2 - 1 = 7 [0b111]). MPC555 MPC556 MEMORY CONTROLLER MOTOROLA USER’S MANUAL Rev. 15 October 2000...
Page 385 Note: Following a system reset, the ATM bits are cleared in DMOR, except the ATM2 bit. This means that only data accesses are dual mapped. Refer to the address types definition in Table 9-8. 13:31 — Reserved MPC555 MPC556 MEMORY CONTROLLER MOTOROLA USER’S MANUAL Rev. 15 October 2000 10-33 For More Information On This Product, Go to: www.freescale.com...
Page 386 Freescale Semiconductor, Inc. MPC555 MPC556 MEMORY CONTROLLER MOTOROLA USER’S MANUAL Rev. 15 October 2000 10-34 For More Information On This Product, Go to: www.freescale.com...
Page 387: General Features
• Each of the four regions supports the following attributes: • Access protection: user or supervisor • Guarded attribute: speculative or non-speculative • Enable/disable option • Read only option MPC555 / MPC556 L-BUS TO U-BUS INTERFACE (L2U) MOTOROLA USER’S MANUAL Rev. 15 October 2000...
Page 388: L2U Block Diagram
11.4 Modes Of Operation The L2U Module can operate in the following modes: • Normal Mode • Reset Operation • Factory Test Mode • Peripheral Mode MPC555 MPC556 L-BUS TO U-BUS INTERFACE (L2U) MOTOROLA USER’S MANUAL Rev. 15 October 2000...
Page 389: Normal Mode
The external master can also access the internal PowerPC special registers that are located in L2U. In order to access one of these PowerPC registers the EMCR[CONT] bit in the USIU must be cleared. MPC555 MPC556 L-BUS TO U-BUS INTERFACE (L2U) MOTOROLA USER’S MANUAL...
Page 390: Data Memory Protection
Any ac- cess that matches the specific region within its appropriate size, as defined by the region size field (RS) of the region attribute register, sets a match indication. MPC555 MPC556 L-BUS TO U-BUS INTERFACE (L2U) MOTOROLA USER’S MANUAL...
Page 391: Associated Registers
The registers are also accessed by an external master when EMCR[CONT] = 0. See 11.8 L2U Programming Model for register diagrams and bit descriptions. MPC555 MPC556 L-BUS TO U-BUS INTERFACE (L2U) MOTOROLA USER’S MANUAL Rev. 15 October 2000...
Page 392: Region Base Address Example
It is the user’s responsibility to program only legal region sizes. The L2U does not check whether the value is legal. If the user programs an illegal region size, the region calculation may not be successful. MPC555 MPC556 L-BUS TO U-BUS INTERFACE (L2U) MOTOROLA USER’S MANUAL...
Page 393: L-Bus Memory Access Violations
A store-with-reservation request by the CPU clears the reservation flag. A store request by the CPU does not clear the flag. A store request by some other master to the reservation address clears the reservation flag. MPC555 MPC556 L-BUS TO U-BUS INTERFACE (L2U) MOTOROLA USER’S MANUAL...
Page 394: Reserved Location (Bus) And Possible Actions
L2U depends on the USIU or the UIMB to provide status of res- ervation on external bus and the IMB3 respectively. Table 11-2 lists all reservation protocol cases supported by the L2U snooping logic. MPC555 MPC556 L-BUS TO U-BUS INTERFACE (L2U) MOTOROLA USER’S MANUAL...
Page 395: L-Bus Show Cycle Support
When show cycles are enabled in the L2U module, there is a performance penalty on the L-bus. This occurs because the L2U module does not support more than one ac- cess being processed at any time. To ensure that only one access at a time can be MPC555 MPC556 L-BUS TO U-BUS INTERFACE (L2U) MOTOROLA USER’S MANUAL...
Page 396: Show Cycle Protocol
U-bus again. 5. When the L2U module has U-bus data bus grant, it drives the data phase ter- mination handshakes on the U-bus. 6. Releases the L-bus MPC555 MPC556 L-BUS TO U-BUS INTERFACE (L2U) MOTOROLA USER’S MANUAL...
Page 397: L-Bus Read Show Cycle Flow
• The L2U does not show cycle any L-bus addresses that fall in the L-bus SRAM address space if the SRAM Protection [SP] bit is set in the L2U_MCR. Table 11-4 summarizes the L2U show cycle support. MPC555 MPC556 L-BUS TO U-BUS INTERFACE (L2U) MOTOROLA USER’S MANUAL...
Page 398: L2U Programming Model
The L2U control registers control the L2U bus interface and the DMPU. They are ac- cessible via the MPC555 / MPC556 mtspr and mfspr instructions. They are also ac- cessible by an external master when EMCR[CONT] bit is cleared. L2U control registers are accessible from both the L-bus side and the U-bus side in one clock cy- cle.
Page 399: U-Bus Access
The L2U module configuration register (L2U_MCR) is used to control the L2U module operation. L2U_MCR — L2U Module Configuration Register SPR 568 LSHOW RESERVED RESET: RESERVED RESET: MPC555 MPC556 L-BUS TO U-BUS INTERFACE (L2U) MOTOROLA USER’S MANUAL Rev. 15 October 2000 11-13 For More Information On This Product, Go to: www.freescale.com...
Page 400: Region Base Address Registers (L2U_Rbax)
Region base address. The RBA field provides the base address of the region. The region base 0:19 address should start on the block boundary for the corresponding block size attribute specified in the region attribute register (L2U_RAx). 20:31 — Reserved MPC555 MPC556 L-BUS TO U-BUS INTERFACE (L2U) MOTOROLA USER’S MANUAL Rev. 15 October 2000 11-14 For More Information On This Product, Go to: www.freescale.com...
Page 401: Region Attribute Registers (L2U_Rax)
The global region attribute register defines the protection attributes associated with the memory region which is not protected under the four DMPU regions. This register also provides enable/disable control for the four DMPU regions. MPC555 MPC556 L-BUS TO U-BUS INTERFACE (L2U) MOTOROLA USER’S MANUAL...
Page 402 Reserved Guarded attribute 0 = Not guarded from speculative accesses 1 = Guarded from speculative accesses 26:31 — Reserved MPC555 MPC556 L-BUS TO U-BUS INTERFACE (L2U) MOTOROLA USER’S MANUAL Rev. 15 October 2000 11-16 For More Information On This Product,...
Page 403: Features
Modules on the IMB3 bus can only be reset by SRESET. Some mod- ules may have a module reset, also. The user should not perform instruction fetches from modules on the IMB. MPC555 / MPC556 U-BUS TO IMB3 BUS INTERFACE (UIMB) MOTOROLA USER’S MANUAL...
Page 404: Uimb Block Diagram
HSPEED Functionality IMB bus frequency is the same as U-bus frequency. IMB bus frequency is half that of the U-bus frequency. IMB clock is not generated. MPC555 MPC556 U-BUS TO IMB3 BUS INTERFACE (UIMB) MOTOROLA USER’S MANUAL Rev. 15 October 2000...
Page 405: Interrupt Operation
USIU through the UIMB interface. The UIMB interrupt synchronizer latches the Interrupts from the IMB3 and drives them onto the U-bus, where they are latched by the USIU interrupt controller. MPC555 MPC556 U-BUS TO IMB3 BUS INTERFACE (UIMB) MOTOROLA USER’S MANUAL...
Page 406: Interrupt Sources And Levels On Imb
Interrupt synchronizer will perform. The IRQMUX field can select time-multiplexing protocols for 8, 16, 24 or 32 interrupt sources. These protocols would take one, two, three or four clocks, respec- tively. MPC555 MPC556 U-BUS TO IMB3 BUS INTERFACE (UIMB) MOTOROLA USER’S MANUAL...
Page 407: Time-Multiplexing Protocol For Irq Pins
Latch 0:15 IMB interrupt levels 00, 01, 10, 00, 01, 10,..Latch 0:23 IMB interrupt levels 00, 01, 10, 11, 00, 01, 10, 11,..Latch 0:31 IMB interrupt levels MPC555 MPC556 U-BUS TO IMB3 BUS INTERFACE (UIMB) MOTOROLA USER’S MANUAL Rev.
Page 408: Interrupt Synchronizer
LVL 8-31 RESET State Machine IMBCLOCK U-bus Data[0:31] ILBS [0:1] Figure 12-6 Interrupt Synchronizer Block diagram MPC555 MPC556 U-BUS TO IMB3 BUS INTERFACE (UIMB) MOTOROLA USER’S MANUAL Rev. 15 October 2000 12-6 For More Information On This Product, Go to: www.freescale.com...
Page 409: Programming Model
1.3 MPC555 / MPC556 Address Map, this block be- gins at offset 0x30 7F80 from the start of the MPC555 / MPC556 internal memory map (the last 128-byte sub-block of the UIMB interface memory map). Table 12-5 UIMB Interface Register Map...
Page 410: Test Control Register (Utstcreg)
LVL9 LVL0 LVL11 LVL12 LVL13 LVL14 LVL15 HRESET: LVL16 IRQ17 LVL18 LVL19 LVL20 LVL21 LVL22 LVL23 LVL24 LVL25 LVL26 LVL27 LVL28 LVL29 LVL30 LVL31 HRESET: MPC555 MPC556 U-BUS TO IMB3 BUS INTERFACE (UIMB) MOTOROLA USER’S MANUAL Rev. 15 October 2000...
Page 411 Description Pending interrupt request level. Accessible only in supervisor mode. LVLx identifies the interrupt 0:31 LVLx source as UIMB LVLx, where x is the interrupt number. MPC555 MPC556 U-BUS TO IMB3 BUS INTERFACE (UIMB) MOTOROLA USER’S MANUAL Rev. 15 October 2000...
Page 412 Freescale Semiconductor, Inc. MPC555 MPC556 U-BUS TO IMB3 BUS INTERFACE (UIMB) MOTOROLA USER’S MANUAL Rev. 15 October 2000 12-10 For More Information On This Product, Go to: www.freescale.com...
Page 413: Overview
Freescale Semiconductor, Inc. SECTION 13 QUEUED ANALOG-TO-DIGITAL CONVERTER MODULE-64 The MPC555 / MPC556 includes two independent queued analog-to-digital converter (QADC64) modules. For details of QADC64 operation not included in this section, re- fer to the QADC Reference Manual (QADCRM/AD). 13.1 Overview The QADC64 consists of an analog front-end and a digital control subsystem, which includes an intermodule bus (IMB3) interface block.
Page 414: Features
(including internal channels). All of the channel pins can also be used as general-purpose digital port pins. The following paragraphs describe QADC64 pin functions. Figure 13-2 shows the QADC64 module pins. MPC555 MPC556 QUEUED ANALOG-TO-DIGITAL CONVERTER MODULE-64 MOTOROLA USER’S MANUAL Rev. 15 October 2000 13-2 For More Information On This Product, Go to: www.freescale.com...
Page 415: Port A Pin Functions
Port A pins are referred to as PQA when used as a bidirectional 8-bit digital input/out- put port. These eight pins may be used for general-purpose digital input signals or dig- ital output signals. MPC555 MPC556 QUEUED ANALOG-TO-DIGITAL CONVERTER MODULE-64 MOTOROLA USER’S MANUAL...
Page 416: Port B Pin Functions
The multiplexed address output signals MA[2:0] can be used as multiplex address output bits or as general-purpose I/O. MPC555 MPC556 QUEUED ANALOG-TO-DIGITAL CONVERTER MODULE-64 MOTOROLA USER’S MANUAL...
Page 417: Multiplexed Analog Input Pins
A pins. 13.3.9 Digital Supply Pins and V provide the power for the digital portions of the QADC64, and for all other digital MCU modules. MPC555 MPC556 QUEUED ANALOG-TO-DIGITAL CONVERTER MODULE-64 MOTOROLA USER’S MANUAL Rev. 15 October 2000...
Page 418: Qadc64 Bus Interface
CCWs into RAM or read results from RAM. 13.5.2 Freeze Mode The QADC64 enters freeze mode when background debug mode is enabled and a breakpoint is processed. This is indicated by assertion of the FREEZE line on the MPC555 MPC556 QUEUED ANALOG-TO-DIGITAL CONVERTER MODULE-64 MOTOROLA USER’S MANUAL Rev.
Page 419: Supervisor/Unrestricted Address Space
QADC64 port pins, when used as general-purpose input, are conditioned by a syn- chronizer with an enable feature. The synchronizer is not enabled until the QADC64 decodes an IMB bus cycle which addresses the port data register to minimize the high- MPC555 MPC556 QUEUED ANALOG-TO-DIGITAL CONVERTER MODULE-64 MOTOROLA USER’S MANUAL...
Page 420: Port Data Register
When a DDRQA bit is set to one and the pin is selected for analog con- version, the voltage sampled is that of the output digital driver as influenced by the load. NOTE MPC555 MPC556 QUEUED ANALOG-TO-DIGITAL CONVERTER MODULE-64 MOTOROLA USER’S MANUAL Rev.
Page 421: External Multiplexing Operation
These outputs are connected to all four multiplexers. The analog output of each mul- tiplexer is each connected to one of four separate QADC64 inputs — ANw, ANx, ANy, and ANz. MPC555 MPC556 QUEUED ANALOG-TO-DIGITAL CONVERTER MODULE-64 MOTOROLA USER’S MANUAL Rev.
Page 422: Analog Input Channels
A maximum of 16 analog channels are supported by the internal multiplexing circuitry of the converter. Table 13-2 shows the total number of analog in- put channels supported with zero to four external multiplexers. MPC555 MPC556 QUEUED ANALOG-TO-DIGITAL CONVERTER MODULE-64 MOTOROLA USER’S MANUAL Rev. 15 October 2000...
Page 423: Analog Subsystem
DAC array, and through the analog comparator. The output of the com- parator feeds into the SAR. Figure 13-4 shows a block diagram of the QADC64 analog submodule. MPC555 MPC556 QUEUED ANALOG-TO-DIGITAL CONVERTER MODULE-64 MOTOROLA USER’S MANUAL Rev.
Page 424: Conversion Cycle Times
13.0 µs with a 2-MHz QCLK. Figure 13-5 illustrates the timing for conversions. This diagram assumes a final sampling period of two QCLK cycles. MPC555 MPC556 QUEUED ANALOG-TO-DIGITAL CONVERTER MODULE-64 MOTOROLA USER’S MANUAL Rev. 15 October 2000...
Page 425: Amplifier Bypass Mode Conversion Timing
(2, 4, 8, 16) 10 CYCLES QCLK SUCCESSIVE APPROXIMATION RESOLUTION SAMPLE TIME SEQUENCE Figure 13-6 Bypass Mode Conversion Timing MPC555 MPC556 QUEUED ANALOG-TO-DIGITAL CONVERTER MODULE-64 MOTOROLA USER’S MANUAL Rev. 15 October 2000 13-13 For More Information On This Product, Go to: www.freescale.com...
Page 426: Front-End Analog Multiplexer
Each CCW specifies the conversion of one input channel. Depending on the applica- tion, one or two queues can be established in the CCW table. A queue is a scan se- quence of one or more input channels. By using a pause mechanism, sub-queues can MPC555 MPC556 QUEUED ANALOG-TO-DIGITAL CONVERTER MODULE-64 MOTOROLA USER’S MANUAL...
Page 427: Queue Priority
CCW format and an example of using pause to create sub- queues. Queue 1 is shown with four CCWs in each sub-queue and queue 2 has two CCWs in each sub-queue. MPC555 MPC556 QUEUED ANALOG-TO-DIGITAL CONVERTER MODULE-64 MOTOROLA USER’S MANUAL...
Page 428: Qadc64 Queue Operation With Pause
(after the queue completion flag is set), causes execution to continue with the first sub-queue, starting with the first CCW in the queue. MPC555 MPC556 QUEUED ANALOG-TO-DIGITAL CONVERTER MODULE-64 MOTOROLA USER’S MANUAL Rev.
Page 429: Queue Boundary Conditions
• The pause bit is set in CCW5 and the channel 63 (EOQ) code is in CCW6 • The pause bit is set in CCW63 • During queue 1 operation, the pause bit is set in CCW14 and BQ2 points to CCW15 MPC555 MPC556 QUEUED ANALOG-TO-DIGITAL CONVERTER MODULE-64 MOTOROLA USER’S MANUAL Rev.
Page 430: Scan Modes
When the application software wants to execute a single pass through a sequence of conversions defined by a queue, a single-scan queue operating mode is selected. By programming the MQ field in QACR1 or QACR2, the following modes can be selected: MPC555 MPC556 QUEUED ANALOG-TO-DIGITAL CONVERTER MODULE-64 MOTOROLA USER’S MANUAL...
Page 431 QADC64 immediately begins execution of the first CCW in the queue. If a pause occurs, another trigger event is generated internally, and then exe- cution continues without pausing. MPC555 MPC556 QUEUED ANALOG-TO-DIGITAL CONVERTER MODULE-64 MOTOROLA USER’S MANUAL Rev.
Page 432 While the gate is open, queue 1 executes one time. Each CCW is read and the indi- cated conversions are performed until an end-of-queue condition is encountered. When queue 1 completes, the QADC64 sets the completion flag (CF1) and clears the MPC555 MPC556 QUEUED ANALOG-TO-DIGITAL CONVERTER MODULE-64 MOTOROLA USER’S MANUAL...
Page 433: Continuous-Scan Modes
13.10.3.4 Continuous-Scan Modes When the application software wants to execute multiple passes through a sequence of conversions defined by a queue, a continuous-scan queue operating mode is se- MPC555 MPC556 QUEUED ANALOG-TO-DIGITAL CONVERTER MODULE-64 MOTOROLA USER’S MANUAL Rev.
Page 434 While the time to internally generate and act on a trigger event is very short, software can momentarily read the status conditions, indicating that the queue is idle. The trig- ger overrun flag is never set while in the software initiated continuous-scan mode. MPC555 MPC556 QUEUED ANALOG-TO-DIGITAL CONVERTER MODULE-64 MOTOROLA USER’S MANUAL...
Page 435 Software initialization is not needed between trigger events. If a pause in a CCW is encountered, the pause flag will not set, and execution continues without pausing. MPC555 MPC556 QUEUED ANALOG-TO-DIGITAL CONVERTER MODULE-64 MOTOROLA USER’S MANUAL...
Page 436: Qadc64 Clock (Qclk) Generation
13.10.4 QADC64 Clock (QCLK) Generation Figure 13-8 is a block diagram of the clock subsystem. The QCLK provides the timing for the A/D converter state machine, which controls the timing of the conversion. The MPC555 MPC556 QUEUED ANALOG-TO-DIGITAL CONVERTER MODULE-64 MOTOROLA USER’S MANUAL Rev.
Page 437 A change in the prescaler value while a conversion is in progress is likely to corrupt the result from any conversion in progress. There- fore, any prescaler write operation should be done only when both queues are in the disabled modes. MPC555 MPC556 QUEUED ANALOG-TO-DIGITAL CONVERTER MODULE-64 MOTOROLA USER’S MANUAL Rev.
Page 438: Qadc64 Clock Subsystem Functions
(prescaler clock high time) field in QACR0, and selects the basic low phase of QCLK with the prescaler clock low time (PSL) field. The combination of the PSH and PSL pa- rameters establishes the frequency of the QCLK. MPC555 MPC556 QUEUED ANALOG-TO-DIGITAL CONVERTER MODULE-64 MOTOROLA USER’S MANUAL...
Page 439 High QCLK Time = (7 + 1) ÷ 32 x 10 = 250 ns Low QCLK Time = (7 + 1) ÷ 32 x 10 = 250 ns MPC555 MPC556 QUEUED ANALOG-TO-DIGITAL CONVERTER MODULE-64 MOTOROLA USER’S MANUAL Rev. 15 October 2000...
Page 440: Qadc64 Clock Programmability Examples
IMB clock. It also shows that when PSL = 7, the QCLK remains low for eight IMB clock cycles. In Example 2, PSH = 7, the QCLK remains high for eight MPC555 MPC556 QUEUED ANALOG-TO-DIGITAL CONVERTER MODULE-64 MOTOROLA USER’S MANUAL...
Page 441: Periodic/Interval Timer
QACR1 and/or QACR2. Figure 13-10 displays the QADC64 interrupt flow. MPC555 MPC556 QUEUED ANALOG-TO-DIGITAL CONVERTER MODULE-64 MOTOROLA USER’S MANUAL Rev. 15 October 2000...
Page 442: Interrupt Sources
CPU. If a new event occurs between the time that the register is read and the time that it is written, the associated flag is not cleared. MPC555 MPC556 QUEUED ANALOG-TO-DIGITAL CONVERTER MODULE-64 MOTOROLA USER’S MANUAL...
Page 443: Interrupt Register
“A” or “B” for the QADC64_A or QADC64_B module, respec- tively. The address offset shown is from the base address of the module. Refer to MPC555 / MPC556 Address Map to locate each QADC64 module in the MPC555 / MPC556 memory map. MPC555...
Page 444 (QADC64TEST). The global registers are always defined to be in supervisor data space. The CPU allows software to establish the global registers in supervisor data space and the remaining registers and tables in user space. MPC555 MPC556 QUEUED ANALOG-TO-DIGITAL CONVERTER MODULE-64 MOTOROLA USER’S MANUAL...
Page 445: Qadc64 Module Configuration Register
13.12.3 QADC64 Interrupt Register QADC64INT — QADC64 Interrupt Register 0x30 4804 0x30 4C04 RESERVED IRL1 IRL2 RESET: MPC555 MPC556 QUEUED ANALOG-TO-DIGITAL CONVERTER MODULE-64 MOTOROLA USER’S MANUAL Rev. 15 October 2000 13-33 For More Information On This Product, Go to: www.freescale.com...
Page 446: Port A/B Data Register
Port B pins are referred to as PQB when used as an 8-bit input-only port. Port B can also be used 8:15 PQB[0:7] for non-multiplexed (AN[51:48])/AN[3:0]) and multiplexed (ANz, ANy, ANx, ANw) analog inputs. MPC555 MPC556 QUEUED ANALOG-TO-DIGITAL CONVERTER MODULE-64 MOTOROLA USER’S MANUAL Rev.
Page 447: Port Data Direction Register
QADC64, and not changed afterwards. QACR0 — QADC64 Control Register 0 0x30 480A 0x30 4C0A RESERVED RESERVED RESET: MPC555 MPC556 QUEUED ANALOG-TO-DIGITAL CONVERTER MODULE-64 MOTOROLA USER’S MANUAL Rev. 15 October 2000 13-35 For More Information On This Product, Go to: www.freescale.com...
Page 448: Qadc64 Control Register 1 (Qacr1)
Note that this bit location is maintained for software compatibility with previous versions of the QADC64. It serves no functional benefit in the MPC555 / MPC556 and is not operational. Prescaler clock low time. The PSL field selects the QCLK low time in the prescaler. PSL value...
Page 449 Queue 1 operating mode. The MQ1 field selects the queue operating mode for queue 1. Table 13-13 shows the different queue 1 operating modes. 8:15 — Reserved MPC555 MPC556 QUEUED ANALOG-TO-DIGITAL CONVERTER MODULE-64 MOTOROLA USER’S MANUAL Rev. 15 October 2000 13-37 For More Information On This Product,...
Page 450: Qadc64 Control Register 2 (Qacr2)
Control register two is the mode control register for the operation of queue 2. Software specifies the queue operating mode of queue 2, and may enable a completion and/or a pause interrupt. All control register fields are read/write data, except the SSE2 bit, MPC555 MPC556 QUEUED ANALOG-TO-DIGITAL CONVERTER MODULE-64 MOTOROLA USER’S MANUAL...
Page 451 The BQ2 field also indicates the end of queue 1 and thus creates an end-of-queue condition 9:15 for queue 1. Setting BQ2 to any value ≥ 64 (0b1000000) allows the entire RAM space for queue 1 CCWs. MPC555 MPC556 QUEUED ANALOG-TO-DIGITAL CONVERTER MODULE-64 MOTOROLA USER’S MANUAL Rev.
Page 452: Qadc64 Status Register 0 (Qasr0)
QASR0 contains information about the state of each queue and the current A/D con- version. Except for the four flag bits (CF1, PF1, CF2, and PF2) and the two trigger overrun bits (TOR1 and TOR2), all of the status register fields contain read-only data. MPC555 MPC556 QUEUED ANALOG-TO-DIGITAL CONVERTER MODULE-64 MOTOROLA USER’S MANUAL...
Page 453 0 = No unexpected queue 2 trigger events have occurred 1 = At least one unexpected queue 2 trigger event has occurred MPC555 MPC556 QUEUED ANALOG-TO-DIGITAL CONVERTER MODULE-64 MOTOROLA USER’S MANUAL Rev.
Page 454: Qadc64 Status Register 1 (Qasr1)
The QASR1 contains two fields: command word pointers for queue 1 and queue 2. QASR1 — Status Register1 0x30 4812 0x30 4C12 RESERVED CWPQ1 RESERVED CWPQ2 RESET: MPC555 MPC556 QUEUED ANALOG-TO-DIGITAL CONVERTER MODULE-64 MOTOROLA USER’S MANUAL Rev. 15 October 2000 13-42 For More Information On This Product, Go to: www.freescale.com...
Page 455: Conversion Command Word Table
To dedicate the entire CCW table to queue 2, software must do the following: • Program queue 1 to be in the disabled mode • Program BQ2 to be the first location in the CCW table. MPC555 MPC556 QUEUED ANALOG-TO-DIGITAL CONVERTER MODULE-64 MOTOROLA USER’S MANUAL...
Page 456: Qadc64 Conversion Queue Operation
CCWs in a queue or sub-queue. An external trigger is only one of the possible trig- ger events. A scan sequence may be initiated by the following: • A software command MPC555 MPC556 QUEUED ANALOG-TO-DIGITAL CONVERTER MODULE-64 MOTOROLA USER’S MANUAL Rev.
Page 457 CCW in progress, and the queue 1 execution be- gins. When queue 1 execution is completed, queue 2 conversions restart with the first CCW entry in queue 2 or the first CCW of the queue 2 sub-queue being ex- MPC555 MPC556 QUEUED ANALOG-TO-DIGITAL CONVERTER MODULE-64 MOTOROLA USER’S MANUAL...
Page 458 CCW entry. CCW — Conversion Command Word Table 0x30 4A00 – 0x30 4A7E 0x30 4E00 – 0x30 4E7E RESERVED CHAN RESET: MPC555 MPC556 QUEUED ANALOG-TO-DIGITAL CONVERTER MODULE-64 MOTOROLA USER’S MANUAL Rev. 15 October 2000 13-46 For More Information On This Product,...
Page 459 Table 13-20 shows the channel number assignments for the non-multiplexed mode. Table 13- shows the channel number assignments for the multiplexed mode. MPC555 MPC556 QUEUED ANALOG-TO-DIGITAL CONVERTER MODULE-64 MOTOROLA USER’S MANUAL Rev. 15 October 2000...
Page 460 — — 111101 — (VRH -VRL)/2 — 111110 — — — End of Queue Code — 111111 MPC555 MPC556 QUEUED ANALOG-TO-DIGITAL CONVERTER MODULE-64 MOTOROLA USER’S MANUAL Rev. 15 October 2000 13-48 For More Information On This Product, Go to: www.freescale.com...
Page 461: Result Word Table
RESULT RESERVED RESET: NOTES: 1. S = Sign bit. The conversion result is signed, left-justified data. Unused bits return zero when read. MPC555 MPC556 QUEUED ANALOG-TO-DIGITAL CONVERTER MODULE-64 MOTOROLA USER’S MANUAL Rev. 15 October 2000 13-49 For More Information On This Product,...
Page 462 0x30 4F80 – 0x30 4FFE RESULT RESERVED RESET: The conversion result is unsigned, left-justified data. Unused bits return zero when read. MPC555 MPC556 QUEUED ANALOG-TO-DIGITAL CONVERTER MODULE-64 MOTOROLA USER’S MANUAL Rev. 15 October 2000 13-50 For More Information On This Product,...
Page 463: Overview
16 entry queues is allocated for the receive and/or transmit oper- ation. 14.2 Block Diagram Figure 14-1 depicts the major components of the QSMCM. MPC555 / MPC556 QUEUED SERIAL MULTI-CHANNEL MODULE MOTOROLA USER’S MANUAL Rev. 15 October 2000...
Page 464: Signal Descriptions
The address offsets shown are from the base address of the QSMCM module. Refer to 1.3 MPC555 / MPC556 Address Map for a diagram of the MPC555 / MPC556 internal memory map. MPC555 MPC556...
Page 465 QSCI1 Control Register (QSCI1CR) 0x30 5028 Table 14-30 for bit descriptions. QSCI1 Status Register (QSCI1SR) 0x30 502A Table 14-31 for bit descriptions. MPC555 MPC556 QUEUED SERIAL MULTI-CHANNEL MODULE MOTOROLA USER’S MANUAL Rev. 15 October 2000 14-3 For More Information On This Product,...
Page 466: Qsmcm Global Registers
The QSMCM global registers contain system parameters used by the QSPI and SCI submodules for interfacing to the CPU and the intermodule bus. The global registers are listed in Table 14-2 QSMCM Global Registers MPC555 MPC556 QUEUED SERIAL MULTI-CHANNEL MODULE MOTOROLA USER’S MANUAL...
Page 467: Low-Power Stop Operation
If a supervisor-only register is accessed in user mode, the module responds as if an ac- cess had been made to an unauthorized register location, and a bus error is generat- MPC555 MPC556 QUEUED SERIAL MULTI-CHANNEL MODULE MOTOROLA USER’S MANUAL...
Page 468: Qsmcm Interrupts
(QDSCI_IL and QSPI_IL). This value determines which interrupt signal (IRQB[0:7]) is driven onto the bus during the programmed time slot. Figure 14-3 shows a block diagram of the interrupt hardware. MPC555 MPC556 QUEUED SERIAL MULTI-CHANNEL MODULE MOTOROLA USER’S MANUAL Rev.
Page 469: Qsmcm Configuration Register (Qsmcmmcr)
This register can be modified only when the CPU is in supervisor mode. QSMCMMCR — QSMCM Configuration Register 0x30 5000 STOP FRZ1 RESERVED SUPV RESERVED IARB RESET: MPC555 MPC556 QUEUED SERIAL MULTI-CHANNEL MODULE MOTOROLA USER’S MANUAL Rev. 15 October 2000 14-7 For More Information On This Product, Go to: www.freescale.com...
Page 470: Qsmcm Test Register (Qtest)
Interrupt level of SCIs ILDSCI 00000 = lowest interrupt level request (level 0) 11111 = highest interrupt level request (level 31) 8:15 — Reserved MPC555 MPC556 QUEUED SERIAL MULTI-CHANNEL MODULE MOTOROLA USER’S MANUAL Rev. 15 October 2000 14-8 For More Information On This Product,...
Page 471: Qsmcm Pin Control Registers
Clearing a bit makes the corresponding pin an input; setting a bit makes the pin an output. DDRQS affects both QSPI function and I/O function. Table 14-10 summarizes the effect of DDRQS bits on QSPI pin function. MPC555 MPC556 QUEUED SERIAL MULTI-CHANNEL MODULE MOTOROLA USER’S MANUAL Rev.
Page 472: Port Qs Data Register (Portqs)
TXDx is a discrete output; when the SCIx receiver is disabled, RXDx is a dis- crete input. Writes to this register affect the pins defined as outputs; reads of this register return the actual value of the pins. MPC555 MPC556 QUEUED SERIAL MULTI-CHANNEL MODULE MOTOROLA USER’S MANUAL...
Page 473: Portqs Pin Assignment Register (Pqspar)
0x30 5016 QPAP QPAP QPAP QPAP QPA- QPAM DDRQS* MOSI RESET: *See bit descriptions in Table 14-11. MPC555 MPC556 QUEUED SERIAL MULTI-CHANNEL MODULE MOTOROLA USER’S MANUAL Rev. 15 October 2000 14-11 For More Information On This Product, Go to: www.freescale.com...
Page 474: Portqs Data Direction Register (Ddrqs)
QDD- QDD- QDD- PQSPAR* PCS3 PCS2 PCS1 PCS0 MOSI MISO SET: *See bit descriptions in Table 14-10. MPC555 MPC556 QUEUED SERIAL MULTI-CHANNEL MODULE MOTOROLA USER’S MANUAL Rev. 15 October 2000 14-12 For More Information On This Product, Go to: www.freescale.com...
Page 475: Queued Serial Peripheral Interface
Several transfer rates, clocking, and interrupt-driven communication options are available. Figure 14-4 is a block diagram of the QSPI. MPC555 MPC556 QUEUED SERIAL MULTI-CHANNEL MODULE MOTOROLA USER’S MANUAL Rev. 15 October 2000...
Page 476: Qspi Block Diagram
An inter-transfer delay of approximately 0.8 to 204 µs (using a 40-MHz IMB clock) can be programmed. The default delay is 17 clocks (0.425 µs at 40 MHz). Programmable delay simplifies the interface to devices that require different delays between transfers. MPC555 MPC556 QUEUED SERIAL MULTI-CHANNEL MODULE MOTOROLA USER’S MANUAL...
Page 477: Qspi Registers
The address offsets shown are from the base address of the QSMCM module. Refer to 1.3 MPC555 / MPC556 Address Map for a diagram of the MPC555 / MPC556 internal memory map. MPC555 MPC556...
Page 478: Qspi Control Register 0
QSPI is enabled disrupts operation. SPCR0 — QSPI Control Register 0 0x30 5018 MSTR BITS CPOL CPHA SPBR RESET: MPC555 MPC556 QUEUED SERIAL MULTI-CHANNEL MODULE MOTOROLA USER’S MANUAL Rev. 15 October 2000 14-16 For More Information On This Product, Go to: www.freescale.com...
Page 479 Bits per Transfer 0000 0001 to 0111 Reserved (defaults to 8) 1000 1001 1010 1011 1100 1101 1110 1111 MPC555 MPC556 QUEUED SERIAL MULTI-CHANNEL MODULE MOTOROLA USER’S MANUAL Rev. 15 October 2000 14-17 For More Information On This Product, Go to: www.freescale.com...
Page 480: Qspi Control Register 1
Rewriting NEWQP in SPCR2 causes ex- ecution to restart at the designated location. Reads of SPCR2 return the current value of the register, not the buffer. MPC555 MPC556 QUEUED SERIAL MULTI-CHANNEL MODULE MOTOROLA USER’S MANUAL...
Page 481: Qspi Control Register 3
SPCR3 — QSPI Control Register 0x30 501E LOOP Reserved HMIE HALT SPSR* RESET: *See bit descriptions in Table 14-18. MPC555 MPC556 QUEUED SERIAL MULTI-CHANNEL MODULE MOTOROLA USER’S MANUAL Rev. 15 October 2000 14-19 For More Information On This Product, Go to: www.freescale.com...
Page 482: Qspi Status Register
SPSR — QSPI Status Register 0x30 501E HAL- SPCR3* SPIF MODF CPTQP *See bit descriptions in Table 14-17. MPC555 MPC556 QUEUED SERIAL MULTI-CHANNEL MODULE MOTOROLA USER’S MANUAL Rev. 15 October 2000 14-20 For More Information On This Product, Go to: www.freescale.com...
Page 483: Qspi Ram
RAM. Receive data is information received from a serial device exter- nal to the MCU. Transmit data is information stored for transmission to an external de- vice. Command data defines transfer parameters. Figure 14-5 shows RAM organization. MPC555 MPC556 QUEUED SERIAL MULTI-CHANNEL MODULE MOTOROLA USER’S MANUAL Rev. 15 October 2000...
Page 484: Receive Ram
RAM. Command RAM consists of 32 bytes. Each byte is divided into two fields. The periph- eral chip-select field, enables peripherals for transfer. The command control field pro- vides transfer options. MPC555 MPC556 QUEUED SERIAL MULTI-CHANNEL MODULE MOTOROLA USER’S MANUAL...
Page 485: Qspi Pins
Table 14-20 identifies the QSPI pins and their functions. Register DDRQS determines whether the pins are designated as input or output. The user must initialize DDRQS for the QSPI to function correctly. MPC555 MPC556 QUEUED SERIAL MULTI-CHANNEL MODULE MOTOROLA USER’S MANUAL Rev.
Page 486: Qspi Operation
CPTQP, the internal pointer is incremented, and then the sequence repeats. Execution continues at the internal pointer address unless the MPC555 MPC556 QUEUED SERIAL MULTI-CHANNEL MODULE MOTOROLA USER’S MANUAL...
Page 487: Enabling, Disabling, And Halting The Spi
QSPI quickly after the current serial transfer is completed. The CPU can disable the QSPI immediately by clearing SPE. However, loss of data from a current serial transfer may result and confuse an external SPI device. MPC555 MPC556 QUEUED SERIAL MULTI-CHANNEL MODULE MOTOROLA USER’S MANUAL...
Page 488: Qspi Interrupts
The CPU must initialize the QSMCM global and pin reg- isters and the QSPI control registers before enabling the QSPI for either mode of op- eration. The command queue must be written before the QSPI is enabled for master MPC555 MPC556 QUEUED SERIAL MULTI-CHANNEL MODULE MOTOROLA USER’S MANUAL...
Page 489: Flowchart Of Qspi Initialization Operation
QSPI Initialization Initialize QSPI Control Registers Initialize QSPI RAM Enable QSPI MSTR = 1 ? Figure 14-6 Flowchart of QSPI Initialization Operation MPC555 MPC556 QUEUED SERIAL MULTI-CHANNEL MODULE MOTOROLA USER’S MANUAL Rev. 15 October 2000 14-27 For More Information On This Product,...
Page 490: Flowchart Of Qspi Master Operation (Part 1)
Programmed? Execute Standard Delay Execute Serial Transfer Store Received Data In RAM Using Queue Pointer Address Figure 14-7 Flowchart of QSPI Master Operation (Part 1) MPC555 MPC556 QUEUED SERIAL MULTI-CHANNEL MODULE MOTOROLA USER’S MANUAL Rev. 15 October 2000 14-28 For More Information On This Product,...
Page 491: Flowchart Of Qspi Master Operation (Part 2)
Chip Selects Is Delay After Transfer Execute Programmed Delay Asserted? Execute Standard Delay Figure 14-8 Flowchart of QSPI Master Operation (Part 2) MPC555 MPC556 QUEUED SERIAL MULTI-CHANNEL MODULE MOTOROLA USER’S MANUAL Rev. 15 October 2000 14-29 For More Information On This Product,...
Page 492: Flowchart Of Qspi Master Operation (Part 3)
Request Interrupt Enable Bit HMIE Set? Is HALT Or FREEZE Asserted? Figure 14-9 Flowchart of QSPI Master Operation (Part 3) MPC555 MPC556 QUEUED SERIAL MULTI-CHANNEL MODULE MOTOROLA USER’S MANUAL Rev. 15 October 2000 14-30 For More Information On This Product,...
Page 493: Flowchart Of Qspi Slave Operation (Part 1)
When SCK Received Store Received Data In RAM Using Queue Pointer Address Write Queue Pointer to CPTQP Status Bits Figure 14-10 Flowchart of QSPI Slave Operation (Part 1) MPC555 MPC556 QUEUED SERIAL MULTI-CHANNEL MODULE MOTOROLA USER’S MANUAL Rev. 15 October 2000 14-31 For More Information On This Product, Go to: www.freescale.com...
Page 494: Flowchart Of Qspi Slave Operation (Part 2)
Figure 14-11 Flowchart of QSPI Slave Operation (Part 2) Normally, the SPI bus performs synchronous bi-directional transfers. The serial clock on the SPI bus master supplies the clock signal SCK to time the transfer of data. Four MPC555 MPC556 QUEUED SERIAL MULTI-CHANNEL MODULE MOTOROLA USER’S MANUAL...
Page 495: Master Mode Operation
PCS[3:0] as outputs. The MISO pin must be configured as an input. After pins are assigned and configured, write appropriate data to the command queue. If data is to be transmitted, write the data to transmit RAM. Initialize the queue pointers as appropriate. MPC555 MPC556 QUEUED SERIAL MULTI-CHANNEL MODULE MOTOROLA USER’S MANUAL...
Page 496: Clock Phase And Polarity
SCK Baud Rate ------------------------- - ¥ SPBR f SYS SPBR ------------------------------------------------------------------------- - 2 SCK Baud Rate Desired ¥ MPC555 MPC556 QUEUED SERIAL MULTI-CHANNEL MODULE MOTOROLA USER’S MANUAL Rev. 15 October 2000 14-34 For More Information On This Product, Go to: www.freescale.com...
Page 497: Delay Before Transfer
A/D converters to com- plete conversion. Writing a value to the DTL field in SPCR1 specifies a delay period. The DT bit in each command RAM byte determines whether the standard delay period MPC555 MPC556 QUEUED SERIAL MULTI-CHANNEL MODULE MOTOROLA USER’S MANUAL...
Page 498: Transfer Length
PCS[0] shares a pin with the slave select SS signal, which initiates slave mode serial transfer. If SS is taken low when the QSPI is in master mode, a mode fault occurs. MPC555 MPC556 QUEUED SERIAL MULTI-CHANNEL MODULE MOTOROLA USER’S MANUAL...
Page 499: Master Wraparound Mode
Before slave mode operation is initiated, DDRQS must be written to direct data flow on the QSPI pins used. Configure the MOSI, SCK and PCS[0]/SS pins as inputs. The MISO pin must be configured as an output. MPC555 MPC556 QUEUED SERIAL MULTI-CHANNEL MODULE MOTOROLA USER’S MANUAL...
Page 500 Slave wraparound mode is enabled by setting the WREN bit in SPCR2. The queue can wrap to pointer address 0x0 or to the address pointed to by NEWQP, depending on the state of the WRTO bit in SPCR2. Slave wraparound operation is identical to master wraparound operation. MPC555 MPC556 QUEUED SERIAL MULTI-CHANNEL MODULE MOTOROLA USER’S MANUAL...
Page 501: Description Of Slave Operation
If more than 16 bits are transferred before negating the PCS[0]/ SS, the QSPI stores the number of bits indicated by BITS in the current receive data segment address, then increments the address and continues storing as described MPC555 MPC556 QUEUED SERIAL MULTI-CHANNEL MODULE MOTOROLA USER’S MANUAL...
Page 502: Slave Wraparound Mode
SPE is not cleared by the QSPI. New receive data overwrites pre- viously received data located in the receive data segment. MPC555 MPC556 QUEUED SERIAL MULTI-CHANNEL MODULE MOTOROLA USER’S MANUAL...
Page 503: Mode Fault
The DSCI has all of the capabilities of previous SCI systems as well as sev- eral significant new features. Figure 14-12 is a block diagram of the SCI transmitter. Figure 14-13 is a block dia- gram of the SCI receiver. MPC555 MPC556 QUEUED SERIAL MULTI-CHANNEL MODULE MOTOROLA USER’S MANUAL Rev. 15 October 2000 14-41 For More Information On This Product, Go to: www.freescale.com...
Page 504: Sci Transmitter Block Diagram
SCxSR STATUS REGISTER TDRE INTERNAL DATA BUS SCI Rx SCI INTERRUPT REQUESTS REQUEST Figure 14-12 SCI Transmitter Block Diagram MPC555 MPC556 QUEUED SERIAL MULTI-CHANNEL MODULE MOTOROLA USER’S MANUAL Rev. 15 October 2000 14-42 For More Information On This Product, Go to: www.freescale.com...
Page 505: Sci Receiver Block Diagram
SCxSR STATUS REGISTER SCI Tx SCI INTERRUPT INTERNAL REQUESTS REQUEST DATA BUS Figure 14-13 SCI Receiver Block Diagram MPC555 MPC556 QUEUED SERIAL MULTI-CHANNEL MODULE MOTOROLA USER’S MANUAL Rev. 15 October 2000 14-43 For More Information On This Product, Go to: www.freescale.com...
Page 506: Sci Registers
SCCxR1 should both be initialized at the same time or before TE and RE are asserted. A single half-word write to SCCxR1 can be used to initialize SCIx and enable the trans- mitter and receiver. MPC555 MPC556 QUEUED SERIAL MULTI-CHANNEL MODULE MOTOROLA USER’S MANUAL...
Page 507: Sci Control Register 0
Changing the value of SCCxR1 bits during a transfer operation can disrupt the trans- fer. Before changing register values, allow the SCI to complete the current transfer, then disable the receiver and transmitter. MPC555 MPC556 QUEUED SERIAL MULTI-CHANNEL MODULE MOTOROLA USER’S MANUAL...
Page 508 1 = SCI transmitter enabled (TXD pin dedicated to SCI transmitter). Receiver Enable 0 = SCI receiver disabled (RXD pin can be used as general-purpose input). 1 = SCI receiver enabled (RXD pin is dedicated to SCI receiver). MPC555 MPC556 QUEUED SERIAL MULTI-CHANNEL MODULE MOTOROLA USER’S MANUAL...
Page 509: Sci Status Register (Scxsr)
SCxDR. SCxSR — SCIx Status Register 0x30 500C, 0x30 5024 RESERVED TDRE RDRF IDLE RESET: MPC555 MPC556 QUEUED SERIAL MULTI-CHANNEL MODULE MOTOROLA USER’S MANUAL Rev. 15 October 2000 14-47 For More Information On This Product, Go to: www.freescale.com...
Page 510 RDRx, the OR flag reflects an operational condition that resulted in a loss of data to RDRx. 0 = RDRF is cleared before new data arrives. 1 = RDRF is not cleared before new data arrives. MPC555 MPC556 QUEUED SERIAL MULTI-CHANNEL MODULE MOTOROLA USER’S MANUAL...
Page 511: Sci Data Register (Scxdr)
SCxDR — SCI Data Register 0x30 500E, 0x30 5026 RESERVED R8/T8 R7/T7 R6/T6 R5/T5 R4/T4 R3/T3 R2/T2 R1/T1 R0/T0 RESET: MPC555 MPC556 QUEUED SERIAL MULTI-CHANNEL MODULE MOTOROLA USER’S MANUAL Rev. 15 October 2000...
Page 512: Sci Pins
• Data frame — A start bit, a specified number of data or information bits, and at least one stop bit. • Idle frame — A frame that consists of consecutive ones. An idle frame has no start bit. MPC555 MPC556 QUEUED SERIAL MULTI-CHANNEL MODULE MOTOROLA USER’S MANUAL...
Page 513: Serial Formats
SCxBR f SYS ------------------------------------------------------ - SCxBR × SCI Baud Rate Desired where SCxBR is in the range {1, 2, 3, ..., 8191}. MPC555 MPC556 QUEUED SERIAL MULTI-CHANNEL MODULE MOTOROLA USER’S MANUAL Rev. 15 October 2000 14-51 For More Information On This Product,...
Page 514: Parity Checking
The shifter output is connected to the TXD pin while the transmitter is operating (TE = 1, or TE = 0 and transmission in progress). Wired-OR operation should be specified when more than one transmitter is used on the same SCI bus. The WOMS bit in MPC555 MPC556 QUEUED SERIAL MULTI-CHANNEL MODULE MOTOROLA USER’S MANUAL...
Page 515 Configure the TXD pin as an output, then write a one to either QDTX1 or QDTX2 of the PORTQS register. See 14.6.1. When the transmitter releases control of the TXD pin, it reverts to driving a logic one output. MPC555 MPC556 QUEUED SERIAL MULTI-CHANNEL MODULE MOTOROLA USER’S MANUAL...
Page 516: Receiver Operation
The bit-time synchronization is done at the be- ginning of each frame so that small differences in the baud rate of the receiver and transmitter are not cumulative. SCIx also synchronizes on all one-to-zero transitions MPC555 MPC556 QUEUED SERIAL MULTI-CHANNEL MODULE MOTOROLA USER’S MANUAL...
Page 517 14-14. This example demonstrates the search for a valid start bit and the synchronization procedure as out- lined above. The possibilities of noise durations greater than one bit-time are not con- sidered in this examples. MPC555 MPC556 QUEUED SERIAL MULTI-CHANNEL MODULE MOTOROLA USER’S MANUAL...
Page 518: Receiver Functional Operation
Noise errors, parity errors, and framing errors can be detected while a data stream is being received. Although error conditions are detected as bits are received, the noise MPC555 MPC556 QUEUED SERIAL MULTI-CHANNEL MODULE MOTOROLA USER’S MANUAL...
Page 519: Idle-Line Detection
SCRQ[0:15]. IDLE is not set again until after at least one frame has been re- ceived (RDRF = 1). This prevents an extended idle interval from causing more than one interrupt. MPC555 MPC556 QUEUED SERIAL MULTI-CHANNEL MODULE MOTOROLA USER’S MANUAL...
Page 520: Receiver Wake-Up
(i.e. transmit and receive operations done via SC1DR). However, if the SCI1 queue feature is enabled (by setting the QTE and/or QRE bits within QSCI1CR) a set of 16 entry queues is allocated for the receive and/or transmit operation. Through soft- MPC555 MPC556 QUEUED SERIAL MULTI-CHANNEL MODULE MOTOROLA USER’S MANUAL...
Page 521: Queued Sci1 Status And Control Registers
14.9.2.1 QSCI1 Control Register QSCI1CR — QSCI1 Control Register 0x30 5028 QTH- QBH- QTHE QTPNT QTSZ RESET: MPC555 MPC556 QUEUED SERIAL MULTI-CHANNEL MODULE MOTOROLA USER’S MANUAL Rev. 15 October 2000 14-59 For More Information On This Product, Go to: www.freescale.com...
Page 522 Queue transfer size. The QTSZ bits allow programming the number of data frames to be trans- 12:15 QTSZ mitted. From 1 (QTSZ = 0b0000) to 16 (QTSZ = 0b1111) data frames can be specified. QTSZ is loaded into QPEND initially or when a wrap occurs. MPC555 MPC556 QUEUED SERIAL MULTI-CHANNEL MODULE MOTOROLA USER’S MANUAL Rev.
Page 523: Qsci1 Status Register
From 1 (QPEND = 0b0000) to 16 (or done, QPEND = 1111) data frames can be specified. 14.9.3 QSCI1 Transmitter Block Diagram The block diagram of the enhancements to the SCI transmitter is shown in Figure 14- MPC555 MPC556 QUEUED SERIAL MULTI-CHANNEL MODULE MOTOROLA USER’S MANUAL Rev.
Page 524: Qsci1 Additional Transmit Operation Features
9-bit registers. All other bits pertaining to the queue should be ignored by software. • Programmable queue up to 16 transmits (SCTQ[0:15]) which may allow for infi- nite and continuous transmits. • Available transmit wrap function to prevent message breaks for transmits greater MPC555 MPC556 QUEUED SERIAL MULTI-CHANNEL MODULE MOTOROLA USER’S MANUAL Rev.
Page 525 SCTQ[0:15]. If the queue is disabled (QTE = 0), the TC bit operates as originally designed. • When the transmit queue is enabled (QTE = 1), writes to the transmit data register (SC1DR) have no effect. MPC555 MPC556 QUEUED SERIAL MULTI-CHANNEL MODULE MOTOROLA USER’S MANUAL...
Page 526: Qsci1 Transmit Flow Chart Implementing The Queue
QPEND = 1111 QTWE = 1 Clear QTWE & QTHE = 0? Set QTHE, QBHE Clear QTE Figure 14-16 Queue Transmit Flow MPC555 MPC556 QUEUED SERIAL MULTI-CHANNEL MODULE MOTOROLA USER’S MANUAL Rev. 15 October 2000 14-64 For More Information On This Product,...
Page 527: Queue Transmit Software Flow
Then Clear QTE and/or TE Than 8 Data Frames on Wrap Read QBHE=1,Write QBHE=0 Write New Data to SCTQ[8:15] DONE Figure 14-17 Queue Transmit Software Flow MPC555 MPC556 QUEUED SERIAL MULTI-CHANNEL MODULE MOTOROLA USER’S MANUAL Rev. 15 October 2000 14-65 For More Information On This Product, Go to: www.freescale.com...
Page 528: Example Qsci1 Transmit For 17 Data Bytes
1000 SCTQ[15] 1111 Load QPEND with QTSZ (0) Clear QTWE Reset QTPNT Figure 14-18 Queue Transmit Example for 17 Data Bytes MPC555 MPC556 QUEUED SERIAL MULTI-CHANNEL MODULE MOTOROLA USER’S MANUAL Rev. 15 October 2000 14-66 For More Information On This Product,...
Page 529: Example Sci Transmit For 25 Data Bytes
SCTQ[15] Load QPEND with QTSZ Clear QTWE Reset QTPNT Write SCTQ[8] Clear QBHE Figure 14-19 Queue Transmit Example for 25 Data Frames MPC555 MPC556 QUEUED SERIAL MULTI-CHANNEL MODULE MOTOROLA USER’S MANUAL Rev. 15 October 2000 14-67 For More Information On This Product,...
Page 530: Qsci1 Receiver Block Diagram
(QRE) bit set by software. When the queue is enabled, software should ig- nore the RDRF bit. • When the queue is disabled (QRE = 0), the SCI functions in single buffer receive mode (as originally designed) and RDRF and OR function as previously defined. MPC555 MPC556 QUEUED SERIAL MULTI-CHANNEL MODULE MOTOROLA USER’S MANUAL...
Page 531 (SC1DR), but it cannot be placed into the receive queue due to either the QTHF or QBHF flag being set (QSCI1SR). Under this condition, the receive queue is dis- abled (QRE = 0). Software may service the receive queue and clear the appropri- MPC555 MPC556 QUEUED SERIAL MULTI-CHANNEL MODULE MOTOROLA USER’S MANUAL...
Page 532 (SC1DR) is still full. The data in the shifter that generated the OR assertion is overwritten by the next received data frame, but the data in the SC1DR is not lost. MPC555 MPC556 QUEUED SERIAL MULTI-CHANNEL MODULE MOTOROLA USER’S MANUAL...
Page 533: Qsci1 Receive Flow Chart Implementing The Queue
Clear QTHF Increment QRPNT Set QTHF QRPNT = 1000? Clear QBHF QRPNT = 0000? Set QBHF Figure 14-21 Queue Receive Flow MPC555 MPC556 QUEUED SERIAL MULTI-CHANNEL MODULE MOTOROLA USER’S MANUAL Rev. 15 October 2000 14-71 For More Information On This Product,...
Page 534: Qsci1 Receive Queue Software Flow Chart
Read SCRQ[8:15] Write QBHF = 0 IDLE = 1? Clear QRE and/or RE To Exit the Queue DONE Figure 14-22 Queue Receive Software Flow MPC555 MPC556 QUEUED SERIAL MULTI-CHANNEL MODULE MOTOROLA USER’S MANUAL Rev. 15 October 2000 14-72 For More Information On This Product,...
Page 535: Example Qsci1 Receive Operation Of 17 Data Frames
SCRQ[15] 1111 SCRQ[15] Read SCRQ[0] Read SCRQ[8:15] Clear QRE/RE Clear QBHF Figure 14-23 Queue Receive Example for 17 Data Bytes MPC555 MPC556 QUEUED SERIAL MULTI-CHANNEL MODULE MOTOROLA USER’S MANUAL Rev. 15 October 2000 14-73 For More Information On This Product,...
Page 536 Freescale Semiconductor, Inc. MPC555 MPC556 QUEUED SERIAL MULTI-CHANNEL MODULE MOTOROLA USER’S MANUAL Rev. 15 October 2000 14-74 For More Information On This Product, Go to: www.freescale.com...
Page 537: Mios1 Features
PWM. Because the MIOS is composed of submodules, it is easily config- urable for different kinds of applications. MIOS1 is the implementation of the MIOS architecture used in the MPC555 / MPC556. The MIOS1 is composed of the following submodules: •...
Page 538 = 40 MHz with 8 bits of resolution and divide-by-4096 prescaler selection: 38.14 Hz (26.2 ms.) — Programmable duty cycle from 0% to 100% — Possible interrupt generation after every period MPC555 MPC556 MODULAR INPUT/OUTPUT SUBSYSTEM (MIOS1) MOTOROLA USER’S MANUAL Rev.
Page 539: Submodule Numbering, Naming And Addressing
The MIOS1 input and output pin names are composed of five fields according to the following convention: • “M” • <submodule short_prefix> • <submodule number> • <pin attribute suffix> (optional) • <bit number> (optional) MPC555 MPC556 MODULAR INPUT/OUTPUT SUBSYSTEM (MIOS1) MOTOROLA USER’S MANUAL Rev. 15 October 2000 15-3 For More Information On This Product, Go to: www.freescale.com...
Page 540: Block Diagram
MMCnC and its input load pin named MMCnL. On the MPC555 / MPC556 MMC6C is input on MDA11 and MMC22C is input on MDA13. The MMC6L is input on MDA12 and MMC22C is input on MDA14.
Page 541: Mios1 Block Diagram
Submodules Unit Submodule MPIO32B0 MPIOSM32 16-bit Port I/O MPIO32B15 IMB3 Clock IMB3 Figure 15-1 MIOS1 Block Diagram MPC555 MPC556 MODULAR INPUT/OUTPUT SUBSYSTEM (MIOS1) MOTOROLA USER’S MANUAL Rev. 15 October 2000 15-5 For More Information On This Product, Go to: www.freescale.com...
Page 542: Mios1 Bus System
The MIOS1 base address is a multiple of the addressable range. The overall address map organization is shown in Figure 15-2. To find the base address of a given implementation, refer to 1.3 MPC555 / MPC556 Address Map. To find the submodule base address, refer to Table 15-36.
Page 543: Mios1 Memory Map
Reserved 0x30 6C44 MIOS1ER1 0x30 6C46 MIOS1RPR1 Reserved 0x30 6C70 MIOS1LVL1 Reserved Figure 15-2 MIOS1 Memory Map MPC555 MPC556 MODULAR INPUT/OUTPUT SUBSYSTEM (MIOS1) MOTOROLA USER’S MANUAL Rev. 15 October 2000 15-7 For More Information On This Product, Go to: www.freescale.com...
Page 544: Mios1 I/O Ports
15.8.1.1 MIOS1 Test and Pin Control Register MIOS1TPCR — Test and Pin Control Register 0x30 6800 TEST RESERVED VFLS RESET: MPC555 MPC556 MODULAR INPUT/OUTPUT SUBSYSTEM (MIOS1) MOTOROLA USER’S MANUAL Rev. 15 October 2000 15-8 For More Information On This Product,...
Page 545: Mios1 Vector Register
0x30 6804 Table 15-4 MIOS1VNR Bit Descriptions Bit(s) Name Description Module number = 1 on the MPC555 / MPC556. The MPC555 / MPC556 implements the MIOS1 module. 8:15 Version number 15.8.1.4 MIOS1 Module Configuration Register MIOS1MCR — MIOS1 Module Configuration Register...
Page 546: Mbism Interrupt Registers
Table 15-8 for bit descriptions. 15.8.2.1 MIOS1 Interrupt Level Register 0 (MIOS1LVL0) This register contains the interrupt level that applies to the submodules number 15 to zero. MPC555 MPC556 MODULAR INPUT/OUTPUT SUBSYSTEM (MIOS1) MOTOROLA USER’S MANUAL Rev. 15 October 2000...
Page 547: Mios1 Interrupt Level Register 1 (Mios1Lvl1)
The signal received from the IRQ pending register is associated with the interrupt level register within the ICS. This level is coded on five bits in this register: three bits repre- sent one of eight levels and the two other represent the four time multiplex slots. Ac- MPC555 MPC556 MODULAR INPUT/OUTPUT SUBSYSTEM (MIOS1) MOTOROLA USER’S MANUAL...
Page 548: Mios Counter Prescaler Submodule (Mcpsm)
Enable MCPSMSCR PREN Figure 15-3 MCPSM Block Diagram 15.9.1 MIOS Counter Prescaler Submodule (MCPSM) Registers Table 15-9 is the address map for the MCPSM submodule. MPC555 MPC556 MODULAR INPUT/OUTPUT SUBSYSTEM (MIOS1) MOTOROLA USER’S MANUAL Rev. 15 October 2000 15-12 For More Information On This Product,...
Page 549: Mcpsm Status/Control Register (Mcpsmcscr)
The MMCSM may also be configured as an event counter, allowing the overflow flag to be set after a predefined number of events (internal clocks or external events), or MPC555 MPC556 MODULAR INPUT/OUTPUT SUBSYSTEM (MIOS1) MOTOROLA USER’S MANUAL...
Page 550 The polarity of the external input pin is also programmable. Refer to Table 15-36 for the MMCSM relative I/O pin implementation. MPC555 MPC556 MODULAR INPUT/OUTPUT SUBSYSTEM (MIOS1) MOTOROLA USER’S MANUAL Rev. 15 October 2000...
Page 551: Mios Modulus Counter Submodule (Mmcsm) Registers
EDGN EDGP MIOB Figure 15-4 MMCSM Block Diagram 15.10.1 MIOS Modulus Counter Submodule (MMCSM) Registers Each of the two MMCSM submodules in the MPC555 / MPC556 includes the register set shown in Table 15-11. Table 15-11 MMCSM Address Map Address...
Page 552: Mmcsm Up-Counter Register (Mmcsmcnt)
The user should not write directly to the address of the MMCSM- SCRD. This register’s address may be reserved for future use and should not be accessed by the software to assure future software compatibility. MPC555 MPC556 MODULAR INPUT/OUTPUT SUBSYSTEM (MIOS1) MOTOROLA USER’S MANUAL...
Page 553: Mmcsm Status/Control Register (Mmcsmscr)
CLS bits are set to select the clock prescaler as the clock source.Table 15-15 gives the clock divide ratio according to the CP values MPC555 MPC556 MODULAR INPUT/OUTPUT SUBSYSTEM (MIOS1) MOTOROLA USER’S MANUAL Rev.
Page 554: Mios Double Action Submodule (Mdasm)
(measurement or genera- tion) is just one 16-bit counter bus count. Refer to Table 15-36 for the MDASM relative I/O pin implementation. MPC555 MPC556 MODULAR INPUT/OUTPUT SUBSYSTEM (MIOS1) MOTOROLA USER’S MANUAL Rev.
Page 555: Mios Double Action Submodule (Mdasm) Registers
Figure 15-5 MDASM Block Diagram 15.11.1 MIOS Double Action Submodule (MDASM) Registers One set of registers is associated with each MDASM submodule. The base address of the particular submodule is shown in the table below. MPC555 MPC556 MODULAR INPUT/OUTPUT SUBSYSTEM (MIOS1) MOTOROLA USER’S MANUAL...
Page 556 0x30 60E4 MDASM28 Status/Control Register Duplicated (MDASMSCRD) 0x30 60E6 MDASM28 Status/Control Register (MDASMSCR) MDASM29 0x30 60E8 MDASM29 Data A Register (MDASMAR) MPC555 MPC556 MODULAR INPUT/OUTPUT SUBSYSTEM (MIOS1) MOTOROLA USER’S MANUAL Rev. 15 October 2000 15-20 For More Information On This Product,...
Page 557: Mdasm Data A Register
15.11.1.2 MDASM Data B Register (MDASMBR) MDASMBR is the data register associated with channel B. Its use varies with the mode of operation. Depending on the mode selected, software access is to register B1 or register B2. MPC555 MPC556 MODULAR INPUT/OUTPUT SUBSYSTEM (MIOS1) MOTOROLA USER’S MANUAL...
Page 558: Mdasm Status/Control Register (Duplicated)
FREN RESERVED RESET: — * Refer to Table 15-16 for a complete list of all the base addresses for the MDASM registers. MPC555 MPC556 MODULAR INPUT/OUTPUT SUBSYSTEM (MIOS1) MOTOROLA USER’S MANUAL Rev. 15 October 2000 15-22 For More Information On This Product,...
Page 559: Mdasm Status/Control Register
In the DIS, IPWM, IPM and IC modes, the FORCA bit is not used and writing to it has no effect. FORCA is cleared by reset and is always read as zero. Writing a one to both FORCA and FORCB simultaneously resets the output flip-flop. MPC555 MPC556 MODULAR INPUT/OUTPUT SUBSYSTEM (MIOS1) MOTOROLA USER’S MANUAL...
Page 560 9:10 the 16-bit counter buses in the MIOS1. NOTE: In the MPC555 / MPC556, only 0b00 (CB6) and 0b01 (CB22) are implemented. — Mode select. These four mode select bits select the mode of operation of the MDASM. To avoid...
Page 561: Mios Pulse Width Modulation Submodule (Mpwmsm)
Next Period Register MPWMA Next Pulse Width Register MPWMB1 FLAG Request Bus MIOB Figure 15-6 MPWMSM Block Diagram MPC555 MPC556 MODULAR INPUT/OUTPUT SUBSYSTEM (MIOS1) MOTOROLA USER’S MANUAL Rev. 15 October 2000 15-25 For More Information On This Product, Go to: www.freescale.com...
Page 562: Mios Pulse Width Modulation Submodule (Mpwmsm) Registers
MPWMSM18 Period Register (MPWMSMPERR) 0x30 6092 MPWMSM18 Pulse Register (MPWMSMPULR) 0x30 6094 MPWMSM18 Count Register (MPWMSMCNTR) 0x30 6096 MPWMSM18 Status/Control Register (MPWMSMSCR) MPC555 MPC556 MODULAR INPUT/OUTPUT SUBSYSTEM (MIOS1) MOTOROLA USER’S MANUAL Rev. 15 October 2000 15-26 For More Information On This Product,...
Page 563: Mpwmsm Period Register (Mpwmsmperr)
MPWMSM registers. Table 15-21 MPWMSMPULR Bit Descriptions Bit(s) Name Description 0:15 Pulse width. These bits contain the binary value of the pulse width to be generated. MPC555 MPC556 MODULAR INPUT/OUTPUT SUBSYSTEM (MIOS1) MOTOROLA USER’S MANUAL Rev. 15 October 2000 15-27 For More Information On This Product, Go to: www.freescale.com...
Page 564: Mpwmsm Counter Register (Mpwmsmcntr)
FREN TRSP RESERVED RESET: — * Refer to Table 15-19 for a complete list of all the base addresses for the MPWMSM registers. MPC555 MPC556 MODULAR INPUT/OUTPUT SUBSYSTEM (MIOS1) MOTOROLA USER’S MANUAL Rev. 15 October 2000 15-28 For More Information On This Product,...
Page 565 — — — Always High — — — — Low Pulse Rising Edge Falling Edge Rising Edge MPC555 MPC556 MODULAR INPUT/OUTPUT SUBSYSTEM (MIOS1) MOTOROLA USER’S MANUAL Rev. 15 October 2000 15-29 For More Information On This Product, Go to: www.freescale.com...
Page 566: Mios 16-Bit Parallel Port I/O Submodule (Mpiosm)
0x30 6106 Reserved 15.13.1.1 MPIOSM Data Register (MPIOSMDR) This read/write register defines the value to be driven to the pad in output mode, for each implemented I/O pin of the MPIOSM. MPC555 MPC556 MODULAR INPUT/OUTPUT SUBSYSTEM (MIOS1) MOTOROLA USER’S MANUAL Rev.
Page 567: Mpiosm Data Direction Register (Mpiosmddr)
15 corresponds to D0. NOTE D[0:4] controls the signals MPIO32B[0:4]. These functions are shared on the MPC555 / MPC556 pins VF[0:2]/MPIO32B[0:2] VFLS[0:1]/MPIO32B[3:4] and can be configured as the alternate function (VF[0:2] and VFLS[0:1]). See 15.8.1.1 MIOS1 Test and Pin Control Register.
Page 568: Mios Interrupt Request Submodule (Mirsm)
15.14.1 MIOS Interrupt Request Submodule (MIRSM) Each submodule that is capable of generating an interrupt can assert a flag line when an event occurs. In the MIOS1 configuration, there are eighteen flag lines and two MIRSMs are needed. MPC555 MPC556 MODULAR INPUT/OUTPUT SUBSYSTEM (MIOS1) MOTOROLA USER’S MANUAL...
Page 569: Mios Interrupt Request Submodule 0 (Mirsm0) Registers
15.14.3 MIOS Interrupt Request Submodule 1 (MIRSM1) Registers for details about the registers in the MIRSM. 15.14.2 MIOS Interrupt Request Submodule 0 (MIRSM0) Registers Table 15-28 shows the registers associated with the MIRSM0 submodule. MPC555 MPC556 MODULAR INPUT/OUTPUT SUBSYSTEM (MIOS1) MOTOROLA USER’S MANUAL Rev. 15 October 2000...
Page 570: Mirsm0 Interrupt Status Register (Mios1Sr0)
Reserved FLG3 MPWMSM3 flag bit FLG2 MPWMSM2 flag bit FLG1 MPWMSM1 flag bit FLG0 MPWMSM0 flag bit MPC555 MPC556 MODULAR INPUT/OUTPUT SUBSYSTEM (MIOS1) MOTOROLA USER’S MANUAL Rev. 15 October 2000 15-34 For More Information On This Product, Go to: www.freescale.com...
Page 571: Mirsm0 Interrupt Enable Register (Mios1Er0)
MIOS1RPR0 — MIRSM0 Request Pending Register 0x30 6C06 RESERVED RESERVED IRP15 IRP14 IRP13 IRP12 IRP11 IRP6 IRP3 IRP2 IRP1 IRP0 RESET: MPC555 MPC556 MODULAR INPUT/OUTPUT SUBSYSTEM (MIOS1) MOTOROLA USER’S MANUAL Rev. 15 October 2000 15-35 For More Information On This Product, Go to: www.freescale.com...
Page 572: Mios Interrupt Request Submodule 1 (Mirsm1) Registers
MIOS1SR1 — MIRSM1 Interrupt Status Register 0x30 6C40 FLG31 FLG30 FLG29 FLG28 FLG27 RESERVED FLG22 RESERVED FLG19 FLG18 FLG17 FLG16 RESET: MPC555 MPC556 MODULAR INPUT/OUTPUT SUBSYSTEM (MIOS1) MOTOROLA USER’S MANUAL Rev. 15 October 2000 15-36 For More Information On This Product,...
Page 573: Mirsm1 Interrupt Enable Register (Mios1Er1)
This read-only register contains interrupt pending bits. Each bit corresponds to a sub- module. A bit that is set indicates that the associated submodule set its flag and that the corresponding enable bit was set. MPC555 MPC556 MODULAR INPUT/OUTPUT SUBSYSTEM (MIOS1) MOTOROLA USER’S MANUAL...
Page 574: Mios1 Function Examples
50 ns to 6.7 s can be mea- sured. Note that a software option is provided to also generate an interrupt after the first edge. MPC555 MPC556 MODULAR INPUT/OUTPUT SUBSYSTEM (MIOS1) MOTOROLA USER’S MANUAL...
Page 575: Mios1 Example: Double Capture Pulse Width Measurement
16-bit Register B1 Capture Interrupt 16-bit Register B2 Trailing Edge Submodule Bus Figure 15-9 MIOS1 Example: Double Capture Pulse Width Measurement MPC555 MPC556 MODULAR INPUT/OUTPUT SUBSYSTEM (MIOS1) MOTOROLA USER’S MANUAL Rev. 15 October 2000 15-39 For More Information On This Product,...
Page 576: Mios1 Input Double Edge Period Measurement
Capture Buses Interrupt 16-bit Register B2 Designated Edge Submodule Bus Figure 15-10 MIOS1 Example: Double Capture Period Measurement MPC555 MPC556 MODULAR INPUT/OUTPUT SUBSYSTEM (MIOS1) MOTOROLA USER’S MANUAL Rev. 15 October 2000 15-40 For More Information On This Product, Go to: www.freescale.com...
Page 577: Mios1 Double Edge Single Output Pulse Generation
16-bit Compare B Compare Interrupt 16-bit Register B2 Trailing Edge Submodule Bus Figure 15-11 MIOS1 Example: Double Edge Output Compare MPC555 MPC556 MODULAR INPUT/OUTPUT SUBSYSTEM (MIOS1) MOTOROLA USER’S MANUAL Rev. 15 October 2000 15-41 For More Information On This Product,...
Page 578: Mios1 Output Pulse Width Modulation With Mdasm
When the software needs to change the output at a regular rate, such as an acceleration curve, the leading edge interrupt gives the software one period time to up- date the new trailing edge time. MPC555 MPC556 MODULAR INPUT/OUTPUT SUBSYSTEM (MIOS1) MOTOROLA USER’S MANUAL...
Page 579: Mios1 Input Pulse Accumulation
15.16 MIOS1 Configuration The complete MIOS1 submodule and pin configuration is shown in Table 15-36. MPC555 MPC556 MODULAR INPUT/OUTPUT SUBSYSTEM (MIOS1) MOTOROLA USER’S MANUAL Rev. 15 October 2000...
Page 580 MPIO32B5 GP I/O MPIO32B6 MPIO32B6 GP I/O MPIO32B7 MPIO32B7 GP I/O MPIO32B8 MPIO32B8 GP I/O MPIO32B9 MPIO32B9 MPC555 MPC556 MODULAR INPUT/OUTPUT SUBSYSTEM (MIOS1) MOTOROLA USER’S MANUAL Rev. 15 October 2000 15-44 For More Information On This Product, Go to: www.freescale.com...
Page 581 Reserved RQSM0 384-391 0x30 6C00 RQSM1 392-399 0x30 6C40 Reserved 400-511 NOTES: 1. GP = General purpose. MPC555 MPC556 MODULAR INPUT/OUTPUT SUBSYSTEM (MIOS1) MOTOROLA USER’S MANUAL Rev. 15 October 2000 15-45 For More Information On This Product, Go to: www.freescale.com...
Page 582 Freescale Semiconductor, Inc. MPC555 MPC556 MODULAR INPUT/OUTPUT SUBSYSTEM (MIOS1) MOTOROLA USER’S MANUAL Rev. 15 October 2000 15-46 For More Information On This Product, Go to: www.freescale.com...
Page 583: Features
Receiver CNRX1 Slave Bus Interface Unit 1. In the MPC555 / MPC556, the CNTX1 and CNRX1 signals are not available. Figure 16-1 TouCAN Block Diagram 16.1 Features Each TouCAN module provides these features: • Full implementation of CAN protocol specification, version 2.0 A/B —...
Page 584: External Pins
The TouCAN module interface to the CAN bus consists of four pins: CANTX0 and CANTX1, which transmit serial data, and CANRX0 and CANRX1, which receive serial In the MPC555 / MPC556, the CNTX1 and CNRX1 signals are not available. NOTE In the MPC555 / MPC556, the CNTX1 and CNRX1 signals are not available.
Page 585: Toucan Architecture
CNRX0 CNRX1 TRANSCEIVER 1. In the MPC555, the CNTX1 and CNRX1 signals are not available. Figure 16-2 Typical CAN Network Each CAN station is connected physically to the CAN bus through a transceiver. The transceiver provides the transmit drive, waveshaping, and receive/compare functions required for communicating on the CAN bus.
Page 586: Common Fields For Extended And Standard Format Frames
Figure 16-4 Standard ID Message Buffer Structure 16.3.1.1 Common Fields for Extended and Standard Format Frames Table 16-1 describes the message buffer fields that are common to both extended and standard identifier format frames. MPC555 MPC556 CAN 2.0B CONTROLLER MODULE MOTOROLA USER’S MANUAL Rev.
Page 587 NOTES: 1. When a matching remote request frame is detected, the code for such a message buffer is changed to be 1110. MPC555 MPC556 CAN 2.0B CONTROLLER MODULE MOTOROLA USER’S MANUAL Rev.
Page 588: Fields For Extended Format Frames
Only one serial message buffer is active at a time, and its function depends upon the operation of the TouCAN at that time. At no time does the user have access to or visibility of these two buffers. MPC555 MPC556 CAN 2.0B CONTROLLER MODULE MOTOROLA USER’S MANUAL...
Page 589: Message Buffer Activation/Deactivation Mechanism
• Two separate masks for buffers 14 and 15 The value of the mask registers should not be changed during normal operation. If the mask register data is changed after the masked identifier of a received message is MPC555 MPC556 CAN 2.0B CONTROLLER MODULE MOTOROLA USER’S MANUAL...
Page 590: Bit Timing
PROPSEG, PSEG1, PSEG2, and the RJW fields which allow the user to configure the bit timing parameters. The prescaler divide register (PRESDIV) allows the user to select the ratio used to derive the S-clock from the IMB clock. The time MPC555 MPC556 CAN 2.0B CONTROLLER MODULE MOTOROLA USER’S MANUAL...
Page 591: Configuring The Toucan Bit Timing
• 8-bit up/down-counter • Increment by eight (Rx error counter also increments by one) • Decrement by one • Avoid decrement when equal to zero MPC555 MPC556 CAN 2.0B CONTROLLER MODULE MOTOROLA USER’S MANUAL Rev. 15 October 2000...
Page 592: Time Stamp
The value of the free-running 16-bit timer is sampled at the beginning of the identifier field on the CAN bus. For a message being received, the time stamp is stored in the time stamp entry of the receive message buffer at the time the message is written into MPC555 MPC556 CAN 2.0B CONTROLLER MODULE MOTOROLA USER’S MANUAL...
Page 593: Toucan Operation
RJW in control registers 1 and 2 (CANCTRL[1:2]) c. Select the S-clock rate by programming the PRESDIV register d. Select the internal arbitration mode (LBUF bit in CANCTRL1) 2. Initialize message buffers MPC555 MPC556 CAN 2.0B CONTROLLER MODULE MOTOROLA USER’S MANUAL Rev.
Page 594: Transmit Process
CAN bus is free, or at the inter-frame space. If there are multiple messages awaiting transmission, this internal arbitration process selects the message buffer from which the next frame is transmitted. MPC555 MPC556 CAN 2.0B CONTROLLER MODULE MOTOROLA USER’S MANUAL...
Page 595: Transmit Message Buffer Deactivation
2. Write the ID_HIGH and ID_LOW words 3. Write the control/status word to mark the receive message buffer as active and empty NOTE Steps one and three are mandatory for data coherency. MPC555 MPC556 CAN 2.0B CONTROLLER MODULE MOTOROLA USER’S MANUAL Rev.
Page 596: Receive Message Buffer Deactivation
If a receive message buffer is deactivated while a message is being transferred into it, the transfer is halted and no interrupt is requested. If this occurs, that receive message buffer may contain mixed data from two different frames. MPC555 MPC556 CAN 2.0B CONTROLLER MODULE MOTOROLA USER’S MANUAL...
Page 597: Locking And Releasing Message Buffers
RTR bit set to one. Once this remote frame is transmitted success- fully, the transmit message buffer automatically becomes a receive message buffer, with the same ID as the remote frame that was transmitted. MPC555 MPC556 CAN 2.0B CONTROLLER MODULE MOTOROLA USER’S MANUAL...
Page 598: Overload Frames
• The TouCAN ignores its Rx pins and drives its Tx pins as recessive • The TouCAN loses synchronization with the CAN bus and the NOTRDY and FRZACK bits in CANMCR are set • The CPU is allowed to read and write the error counter registers MPC555 MPC556 CAN 2.0B CONTROLLER MODULE MOTOROLA USER’S MANUAL...
Page 599: Low-Power Stop Mode
The count continues when STOP is cleared. • To place the TouCAN in low-power stop mode with the self wake mechanism engaged, write to CANMCR with both STOP and SELFWAKE set, and then wait MPC555 MPC556 CAN 2.0B CONTROLLER MODULE MOTOROLA USER’S MANUAL...
Page 600: Auto Power Save Mode
While its clocks are stopped, if the TouCAN senses that any one of the aforementioned conditions is no longer true, it restarts its clocks. The TouCAN then continues to mon- itor these conditions and stops or restarts its clocks accordingly. MPC555 MPC556 CAN 2.0B CONTROLLER MODULE MOTOROLA USER’S MANUAL...
Page 601: Interrupts
Figure 16-5 displays the interrupt levels on IRQ with ILBS. MPC555 MPC556 CAN 2.0B CONTROLLER MODULE MOTOROLA USER’S MANUAL Rev.
Page 602: Programmer's Model
1.3 MPC555 / MPC556 Address Map to locate each TouCAN module in the MPC555 / MPC556 address map. The column labeled “Access” indicates the privilege level at which the CPU must be operating to access the register. A designation of “S” indicates that supervisor mode is required.
Page 603: Toucan Module Configuration Register
Receive Error Counter 0x30 70A6, (RXECTR_x) Transmit Error Counter (TXECTR_x) 0x30 74A6 Table 16-26 for bit descriptions. MPC555 MPC556 CAN 2.0B CONTROLLER MODULE MOTOROLA USER’S MANUAL Rev. 15 October 2000 16-21 For More Information On This Product, Go to: www.freescale.com...
Page 604 MBUFF13 0x30 71D0 — 0x30 71DF(A) TouCAN_A Message Buffer 13. 0x30 75D0 — 0x30 75DF(B) Table 16-3 Table 16-4 for message buffer definitions. MPC555 MPC556 CAN 2.0B CONTROLLER MODULE MOTOROLA USER’S MANUAL Rev. 15 October 2000 16-22 For More Information On This Product,...
Page 605: Toucan Message Buffer Memory Map
0x30 7120, 0x30 7520 , 0x30 7C20 Message Buffer 2 0x30 71FF, 0x30 75FF , 0x30 7CFF Message Buffer 15 Figure 16-6 TouCAN Message Buffer Memory Map MPC555 MPC556 CAN 2.0B CONTROLLER MODULE MOTOROLA USER’S MANUAL Rev. 15 October 2000 16-23 For More Information On This Product, Go to: www.freescale.com...
Page 606 TCNMCR — TouCAN Module Configuration Register 0x30 7080 0x30 7480 WAKE SOFT SELF STOP STOP HALT SUPV RESERVED USED WAKE RESET: MPC555 MPC556 CAN 2.0B CONTROLLER MODULE MOTOROLA USER’S MANUAL Rev. 15 October 2000 16-24 For More Information On This Product, Go to: www.freescale.com...
Page 607: Control Register 0
0 = Registers with access controlled by the SUPV bit are accessible in either user or super- visor privilege mode 1 = Registers with access controlled by the SUPV bit are restricted to supervisor mode MPC555 MPC556 CAN 2.0B CONTROLLER MODULE MOTOROLA USER’S MANUAL...
Page 608: Toucan Test Configuration Register
16.7.3 TouCAN Interrupt Configuration Register CANICR — TouCAN Interrupt Configuration Register 0x30 7084 0x30 7484 RESERVED ILBS RESERVED RESET: MPC555 MPC556 CAN 2.0B CONTROLLER MODULE MOTOROLA USER’S MANUAL Rev. 15 October 2000 16-26 For More Information On This Product, Go to: www.freescale.com...
Page 609: Control Register 1
Transmit pin configuration control. This bit field controls the configuration of the CANTX0 and TXMODE CANTX1 pins. Refer to Table 16-15. 8:15 CANCTRL1 Table 16-16. MPC555 MPC556 CAN 2.0B CONTROLLER MODULE MOTOROLA USER’S MANUAL Rev. 15 October 2000 16-27 For More Information On This Product, Go to: www.freescale.com...
Page 610: Control Register 2
A logic one on the CNRX0 pin is interpreted as a dominant bit; a logic zeroon the CNRX0 pin is interpreted as a recessive bit NOTES: 1. The CNRX1 signal is not available on the MPC555 / MPC556. Table 16-15 Transmit Pin Configuration TXMODE[1:0]...
Page 611: Prescaler Divide Register
1 Time Quantum = 1 Serial Clock (S-Clock) Period 16.7.6 Prescaler Divide Register PRESDIV — Prescaler Divide Register 0x30 7088 0x30 7488 PRESDIV CANCTRL2 RESET: MPC555 MPC556 CAN 2.0B CONTROLLER MODULE MOTOROLA USER’S MANUAL Rev. 15 October 2000 16-29 For More Information On This Product,...
Page 612 The valid programmed values are zero through seven. 13:15 PSEG2 The length of phase buffer segment two is calculated as follows: Phase Buffer Segment 2 = (PSEG2 + 1) Time Quanta MPC555 MPC556 CAN 2.0B CONTROLLER MODULE MOTOROLA USER’S MANUAL Rev.
Page 613: Receive Global Mask Registers
RESET: MID14 MID13 MID12 MID11 MID10 MID9 MID8 MID7 MID6 MID5 MID4 MID3 MID2 MID1 MID0 RESET: MPC555 MPC556 CAN 2.0B CONTROLLER MODULE MOTOROLA USER’S MANUAL Rev. 15 October 2000 16-31 For More Information On This Product, Go to: www.freescale.com...
Page 614: Receive Buffer 14 Mask Registers
This register reflects various error conditions, general status, and has the enable bits for three of the TouCAN interrupt sources. The reported error conditions are those which have occurred since the last time the register was read. A read clears these bits to zero. MPC555 MPC556 CAN 2.0B CONTROLLER MODULE MOTOROLA USER’S MANUAL...
Page 615: Error Counters
1 = When the TouCAN state changes to bus off, this bit is set, and if the BOFFMSK bit in CANCTRL0 is set, an interrupt request is generated. This interrupt is not requested after reset. MPC555 MPC556 CAN 2.0B CONTROLLER MODULE MOTOROLA USER’S MANUAL...
Page 616: Interrupt Mask Register
8:15 IMASKL enables interrupt requests for the corresponding message buffer. NOTE: Bit 15 (LSB) corresponds to message buffer 0. Bit 0 (MSB) corresponds to mesage buffer 15. MPC555 MPC556 CAN 2.0B CONTROLLER MODULE MOTOROLA USER’S MANUAL Rev. 15 October 2000...
Page 617: Interrupt Flag Register
Name Description 0:7, RXECTR, Both counters are read only, except when the TouCAN is in test or debug mode. 8:15 TXECTR MPC555 MPC556 CAN 2.0B CONTROLLER MODULE MOTOROLA USER’S MANUAL Rev. 15 October 2000 16-35 For More Information On This Product,...
Page 618 Freescale Semiconductor, Inc. MPC555 MPC556 CAN 2.0B CONTROLLER MODULE MOTOROLA USER’S MANUAL Rev. 15 October 2000 16-36 For More Information On This Product, Go to: www.freescale.com...
Page 619: Overview
CPU interven- tion. Consequently, for each timer event, the CPU setup and service times are mini- mized or eliminated. The MPC555 / MPC556 contains two independent TPU3s. Figure 17-1 is a simplified block diagram of a single TPU3.
Page 620: Tpu3 Components
Freescale Semiconductor, Inc. The microcode ROM TPU3 functions that are available in the MPC555 / MPC556 are described in APPENDIX D TPU ROM FUNCTIONS. 17.2 TPU3 Components The TPU3 consists of two 16-bit time bases, 16 independent timer channels, a task scheduler, a microengine, and a host interface.
Page 621: Host Interface
(TPURM/AD). 17.3.2 Channel Orthogonality Most timer systems are limited by the fixed number of functions assigned to each pin. All TPU3 channels contain identical hardware and are functionally equivalent in oper- MPC555 MPC556 TIME PROCESSOR UNIT 3 MOTOROLA USER’S MANUAL Rev.
Page 622: Interchannel Communication
Refer to Motorola Pro- gramming Note Using the TPU Function Library and TPU Emulation Mode, (TPUPN00/D), for information about developing custom functions and accessing the MPC555 MPC556 TIME PROCESSOR UNIT 3 MOTOROLA USER’S MANUAL...
Page 623: Tpu3 Interrupts
The rate at which TCR1 is incremented is determined as follows: • The user selects either the standard prescaler (by clearing the enhanced prescal- er enable bit, EPSCKE, in TPUMCR3) or the enhanced prescaler (by setting EPSCKE). MPC555 MPC556 TIME PROCESSOR UNIT 3 MOTOROLA USER’S MANUAL...
Page 624 TCR1 prescaler (which, in turn, takes as input the output of either the standard or enhanced prescaler). Figure 17-3 shows a diagram of the TCR1 prescaler control block. MPC555 MPC556 TIME PROCESSOR UNIT 3 MOTOROLA USER’S MANUAL Rev.
Page 625: Prescaler Control For Tcr2
The TCR2PSCK2 bit in TPUMCR3 determines whether the clock source is divided by two before it is fed into the TCR2 prescaler. The TCR2 field in TPUMCR specifies the value of the prescaler: 1, 2, 4, or 8. Channels using TCR2 have the capability to re- MPC555 MPC556 TIME PROCESSOR UNIT 3 MOTOROLA USER’S MANUAL...
Page 626: Programming Model
(16-bit) or word (32-bit) accesses. The address space of the TPU3 memory map occupies 512 bytes. Unused registers within the 512-byte address space return zeros when read. Table 17-5 shows the TPU3 address map. MPC555 MPC556 TIME PROCESSOR UNIT 3 MOTOROLA USER’S MANUAL Rev.
Page 627 TPU Module Configuration 3 (TPUMCR3) 0x30 442A Table 17-20 for bit descriptions. 0x30 402C Internal Scan Data Register (ISDR) 0x30 442C MPC555 MPC556 TIME PROCESSOR UNIT 3 MOTOROLA USER’S MANUAL Rev. 15 October 2000 17-9 For More Information On This Product,...
Page 628: Tpu Module Configuration Register
TPUMCR — TPU Module Configuration Register 0x30 4000 0x30 4400 STOP TCR1P TCR2P T2CG SUPV PSCK TPU3 T2CSL RESERVED RESET: MPC555 MPC556 TIME PROCESSOR UNIT 3 MOTOROLA USER’S MANUAL Rev. 15 October 2000 17-10 For More Information On This Product, Go to: www.freescale.com...
Page 629 17.3.9 Prescaler Control for TCR2 for details. Reserved. These bits are used for the IARB (interrupt arbitration ID) field in TPU3 implementa- 12:15 — tions that use hardware interrupt arbitration. MPC555 MPC556 TIME PROCESSOR UNIT 3 MOTOROLA USER’S MANUAL Rev. 15 October 2000...
Page 630: Tpu3 Test Configuration Register
17.4.3 Development Support Control Register DSCR — Development Support Control Register 0x30 4004 0x30 4404 HOT4 RESERVED CLKS RESET: MPC555 MPC556 TIME PROCESSOR UNIT 3 MOTOROLA USER’S MANUAL Rev. 15 October 2000 17-12 For More Information On This Product, Go to: www.freescale.com...
Page 631 0 = Breakpoint not enabled 1 = Break if MRL is asserted at beginning of state TDL breakpoint enable 0 = Breakpoint not enabled 1 = Break if TDL is asserted at beginning of state MPC555 MPC556 TIME PROCESSOR UNIT 3 MOTOROLA USER’S MANUAL Rev.
Page 632: Development Support Status Register
17.4.5 TPU3 Interrupt Configuration Register TICR — TPU3 Interrupt Configuration Register 0x30 4008 0x30 4408 RESERVED CIRL ILBS RESERVED RESET: MPC555 MPC556 TIME PROCESSOR UNIT 3 MOTOROLA USER’S MANUAL Rev. 15 October 2000 17-14 For More Information On This Product, Go to: www.freescale.com...
Page 633: Channel Interrupt Enable Register
Encoded 4-bit fields within the channel function select registers specify one of 16 time functions to be executed on the corresponding channel. Encodings for predefined functions will be provided in a subsequent draft of this document. MPC555 MPC556 TIME PROCESSOR UNIT 3 MOTOROLA USER’S MANUAL...
Page 634: Host Sequence Registers
The meaning of the host sequence bits depends on the time func- tion specified. Meanings of host sequence bits and host service request bits for pre- defined time functions will be provided in a subsequent draft of this document. MPC555 MPC556 TIME PROCESSOR UNIT 3 MOTOROLA USER’S MANUAL...
Page 635: Host Service Request Registers
CH 15 CH 14 CH 13 CH 12 CH 11 CH 10 CH 9 CH 8 RESET: MPC555 MPC556 TIME PROCESSOR UNIT 3 MOTOROLA USER’S MANUAL Rev. 15 October 2000 17-17 For More Information On This Product, Go to: www.freescale.com...
Page 636: Channel Priority Registers
Name Description Encoded channel priority levels. Table 17-15 indicates the number of time slots guaranteed for each CH[15:0] channel priority encoding. MPC555 MPC556 TIME PROCESSOR UNIT 3 MOTOROLA USER’S MANUAL Rev. 15 October 2000 17-18 For More Information On This Product,...
Page 637: Channel Interrupt Status Register
0x30 4024, 0x30 4424 Used for factory test only. 17.4.14 Decoded Channel Number Register DCNR — Decoded Channel Number Register 0x30 4026, 0x30 4426 Used for factory test only. MPC555 MPC556 TIME PROCESSOR UNIT 3 MOTOROLA USER’S MANUAL Rev. 15 October 2000...
Page 638: Tpu3 Module Configuration Register 2
0 = TP15 functions as normal TPU3 channel 1 = TP15 pin configured as output disable pin. When TP15 pin is low, all TPU3 output pins are in a high-impedance state, regardless of the pin function. MPC555 MPC556 TIME PROCESSOR UNIT 3 MOTOROLA USER’S MANUAL...
Page 639: Tpu Module Configuration Register 3
17-4. Enhanced pre-scaler enable EPSCKE 0 = Disable enhanced prescaler (use standard prescaler) 1 = Enable enhanced prescaler. IMB clock will be divided by the value in EPSCK field. MPC555 MPC556 TIME PROCESSOR UNIT 3 MOTOROLA USER’S MANUAL Rev. 15 October 2000...
Page 640: Tpu3 Test Registers
RAM. Refer to Table 17-21. Table 17-21 Parameter RAM Address Offset Map Channel Parameter Number MPC555 MPC556 TIME PROCESSOR UNIT 3 MOTOROLA USER’S MANUAL Rev. 15 October 2000 17-22 For More Information On This Product,...
Page 641: Time Functions
Number NOTES: 1. These addresses should be added to 0x30 4000 to derive the com- plete parameter address. 17.5 Time Functions Descriptions of the MPC555 / MPC556 pre-programmed time functions are shown in APPENDIX D TPU ROM FUNCTIONS. MPC555 MPC556...
Page 642 Freescale Semiconductor, Inc. MPC555 MPC556 TIME PROCESSOR UNIT 3 MOTOROLA USER’S MANUAL Rev. 15 October 2000 17-24 For More Information On This Product, Go to: www.freescale.com...
Page 643: Features
— The DPTRAM array acts as a microcode storage for the TPU module. This provides a means executing TPU code out of DPTRAM instead of program- ming it in the TPU ROM. MPC555 / MPC556 DUAL-PORT TPU RAM (DPTRAM) MOTOROLA USER’S MANUAL...
Page 644: Dptram Configuration And Block Diagram
Table 18-1 shows the DPTRAM control and status registers. The addresses shown are offsets from the base address for the module. Refer to 1.3 MPC555 / MPC556 Ad- MPC555 MPC556 DUAL-PORT TPU RAM (DPTRAM) MOTOROLA USER’S MANUAL...
Page 645: Dptram Module Configuration Register (Dptmcr)
Supv Read Only 0x30 000A 18.3.5 MISC Counter (MISCNT) for bit descriptions. address The DPTRAM array occupies the 6-Kbyte block. In the MPC555 / MPC556, the array must be located at the address 0x30 2000. Refer to Figure 1-3 Figure 18-2.
Page 646: Dptram Test Register
Multiple input signature enable. MISEN is readable and writable at any time. The MISC will only operate when this bit is set and the MPC555 / MPC556 is in TPU3 emulation mode. When en- abled, the MISC will continuously cycle through the RAM addresses, reading each and adding MISEN the contents to the MISR.
Page 647: Ram Base Address Register (Rambar)
18.3.3 Ram Base Address Register (RAMBAR) The RAMBAR register is used to specify the 16 MSBs of the starting DPT RAM array location in the memory map. In the MPC555 / MPC556, this register must be pro- gramed to the value 0xFFA0.
Page 648: Misc Counter (Miscnt)
When the RAM array is powered by the VDDSRAM pin of the MCU, access to the RAM array is blocked. Data read from the RAM array during this condition cannot be guar- anteed. Data written to the DPTRAM may be corrupted if switching occurs during a write operation. MPC555 MPC556 DUAL-PORT TPU RAM (DPTRAM) MOTOROLA USER’S MANUAL...
Page 649: Reset Operation
RAM array are not guaranteed. (Refer to SEC- TION 7 RESET for a description of MPC555 / MPC556 reset sources, operation, con- trol, and status.) Reset will also reconfigure some of the fields and bits in the DPTRAM control registers to their default reset state.
Page 650: Freeze Operation
The contents of the RAM are validated using a multiple input signature calculator (MISC). MISC reads of the RAM are performed only when the MPC555 / MPC556 is in emulation mode and the MISC is enabled (MISEN = 1 in the DPTMCR).
Page 651 This ensures that the host reads the most recently generated signature. The MISC can be disabled by clearing the MISEN bit in the DPTMCR. Note that the reset state of the MPC555 / MPC556 MISEN is disabled. MPC555 MPC556...
Page 652 Freescale Semiconductor, Inc. MPC555 MPC556 DUAL-PORT TPU RAM (DPTRAM) MOTOROLA USER’S MANUAL Rev. 15 October 2000 18-10 For More Information On This Product, Go to: www.freescale.com...
Page 653: Introduction
(NVM) to store system program and data. The modules are designed to be used with the unified bus (U-bus). The CMF arrays use Motorola’s one-transistor (MoneT) bit cell technology. The MPC555 / MPC556’s total 448-Kbytes of flash EEPROM non-volatile memory are distributed between two CMF EEPROM modules: a 256-Kbyte array and a 192-Kbyte array.
Page 654: Mpc555 / Mpc556 Cmf Features
ADDR[17:25]. Erasing is performed on one or more of the selected block(s) simultaneously. 19.1.1 MPC555 / MPC556 CMF Features • Motorola’s one-transistor (MoneT) bit cell • Reset configuration stored in special FLASH NVM locations •...
Page 655 This row may be accessed by setting the SIE bit in the module configuration register and accessing the CMF array. The shad- ow information is always in the lowest array block of the CMF array. MPC555 MPC556 CDR MoneT FLASH EEPROM MOTOROLA USER’S MANUAL...
Page 656: Programming Model
CMF EEPROM array while, the second is the array. Figure 19-1 shows the part of the MPC555 / MPC556 memory map involving the CMF arrays and control registers. Refer to 1.3 MPC555 / MPC556 Address Map for the complete memory map.
Page 657: Cmf Eeprom Configuration Register (Cmfmcr)
RESET: DATA[0:7] PROTECT[0:7] RESET: 1. The reset state of bits 6:7 are defined by special FLASH NVM registers. The factory default state is either 0b01 or 0b10. MPC555 MPC556 CDR MoneT FLASH EEPROM MOTOROLA USER’S MANUAL Rev. 15 October 2000...
Page 658 The SUPV[0:7] bits are write protected by the LOCK and CSC bits. Writes will have no effect if LOCK=0 or CSC=1. 0 = Array block M is placed in unrestricted address space 1 = Array block M is placed in supervisor address space (reset value) MPC555 MPC556 CDR MoneT FLASH EEPROM MOTOROLA USER’S MANUAL...
Page 659: Cmf Eeprom Test Register (Cmftst)
SERVE RESERVED RESET: NOTES: 1. The NVR, STE, and GDB bits are not accessible in all revisions of the MPC555 / MPC556 (2K02A mask sets and earlier). 2. The STE bit should always be programmed as a 0. MPC555 MPC556...
Page 660 50 µs Mode 5NL Negative gate ramp (high range) 50 µs Mode 6NL 50 µs max. 48,000 Mode 7NL MPC555 MPC556 CDR MoneT FLASH EEPROM MOTOROLA USER’S MANUAL Rev. 15 October 2000 19-8 For More Information On This Product, Go to: www.freescale.com...
Page 661: Cmf Eeprom High Voltage Control Register (Cmfctl)
CMFCTL — CMF EEPROM High Voltage Control Register 0x2F C808 0x2F C848 SCLKR CLKPE CLKPM PORESET/HRESET: SRESET: BLOCK[0:7] EPEE PORESET/HRESET: SRESET: MPC555 MPC556 CDR MoneT FLASH EEPROM MOTOROLA USER’S MANUAL Rev. 15 October 2000 19-9 For More Information On This Product, Go to: www.freescale.com...
Page 662 The CSC bit is write protected by the SES bit. Writes to CMFCTL will not change CSC if SES = 1. 0 = Configure for normal operation (default value) 1 = Configure to set or clear the CENSOR bits MPC555 MPC556 CDR MoneT FLASH EEPROM MOTOROLA USER’S MANUAL...
Page 663: Cmf Eeprom Array Addressing
This strategy allows the CMF EEPROM to have a two- clock read for an off-page access and one clock for an on-page access. The BIU does not recognize write accesses to the CMF array. MPC555 MPC556 CDR MoneT FLASH EEPROM MOTOROLA USER’S MANUAL...
Page 664: Read Page Buffers
Table 19-8 CMF EEPROM Array Address Fields Bit(s) Field Description The seven high-order address bits of a CMF EEPROM array access (or any MPC555 / — MPC556 internal access) must equal zero. USIU Internal These bits (programmed in the USIU internal memory map register) specify one of eight Mapping locations for the MPC555 / MPC556 internal memory map.
Page 665: Program Page Buffers
Bits in the program page buffers select the non-program state if SES = 0. During a pro- gram margin read, the program buffers update bits to the non-program state for bits that correspond to array bits that the program margin read has determined are pro- grammed. MPC555 MPC556 CDR MoneT FLASH EEPROM MOTOROLA USER’S MANUAL...
Page 666: Array Configuration For Cmf Module A
If SIE=1, then the shadow row is enabled instead of the flash block. Shadow locations 0x00 to 0x03 are reserved for the Internal Flash Reset Configuration word. Shadow locations 0x04 to 0x0F are Reserved by Motorola for possible future use. MPC555 MPC556 CDR MoneT FLASH EEPROM MOTOROLA USER’S MANUAL...
Page 667: Array Configuration For Cmf Module B
The read page buffer address monitor is reset whenever SIE is modified, making the next CMF array access an off-page access. The default reset state of SIE is normal array access (SIE = 0). MPC555 MPC556 CDR MoneT FLASH EEPROM MOTOROLA USER’S MANUAL...
Page 668: Address Range Of Shadow Information
Note that with the exception of bit 20, the bits in the CMFCFIG are identical to those in the USIU hard reset configuration word. Refer to 7.5.2 Hard Reset Configuration Word for descriptions of these bits. MPC555 MPC556 CDR MoneT FLASH EEPROM MOTOROLA USER’S MANUAL Rev.
Page 669: Array Read Operation
This requires one clock to transfer information from the read page buffer onto the data bus. See section 19.2.2 CMF EE- PROM Array Addressing for more information on array accesses. MPC555 MPC556 CDR MoneT FLASH EEPROM MOTOROLA USER’S MANUAL Rev.
Page 670: Programming The Cmf Array
4. Write SES = 1 in the CMFCTL register. NOTE Step 4 can be accomplished with the same write as that in step 3. It is listed as a separate step in the sequence for looping. MPC555 MPC556 CDR MoneT FLASH EEPROM MOTOROLA USER’S MANUAL...
Page 671 This will reduce the time required to program the array. MPC555 MPC556 CDR MoneT FLASH EEPROM MOTOROLA USER’S MANUAL...
Page 672: Program State Diagram
19-4). c. Go back to step 6 to apply additional programming pulses. 11. If more information needs to be programmed, go back to step 2. Reset Figure 19-3 Program State Diagram MPC555 MPC556 CDR MoneT FLASH EEPROM MOTOROLA USER’S MANUAL Rev.
Page 673 During pro- memory map or a soft reset. gramming the array does not respond to any ac- cess. Accesses to the registers are allowed. A write to CMFCTL can change EHV only. MPC555 MPC556 CDR MoneT FLASH EEPROM MOTOROLA USER’S MANUAL Rev.
Page 674: Program Margin Reads
1 = bit does not need further programming 2. A “0” read during the margin read means that the bit does NOT need further programming. A “1” means the bit needs to be programmed further. MPC555 MPC556 CDR MoneT FLASH EEPROM MOTOROLA USER’S MANUAL...
Page 675: Over-Programming
CLKPM, write the pulse width timing control fields for an erase pulse, BLOCK[0:7] to select the blocks to be erased, PE = 1 and SES = 1 in the CMFCTL register. Set the initial MPC555 MPC556 CDR MoneT FLASH EEPROM MOTOROLA USER’S MANUAL...
Page 676 Go back to step 5 to apply additional erase pulses. NOTE After a location has been verified (all bits erased), it is not necessary to verify the location after subsequent erase pulses. Write SES = 0 in the CMFCTL register. MPC555 MPC556 CDR MoneT FLASH EEPROM MOTOROLA USER’S MANUAL Rev.
Page 677: Erase State Diagram
Freescale Semiconductor, Inc. Reset Figure 19-4 Erase State Diagram MPC555 MPC556 CDR MoneT FLASH EEPROM MOTOROLA USER’S MANUAL Rev. 15 October 2000 19-25 For More Information On This Product, Go to: www.freescale.com...
Page 678: Erase Margin Reads
19.6.3 Erasing Shadow Information Words The shadow information words are erased with CMF array block zero. To verify that the shadow information words are erased, the SIE bit in CMFMCR must be set to one MPC555 MPC556 CDR MoneT FLASH EEPROM MOTOROLA USER’S MANUAL...
Page 679: Voltage Control For Programming And Erasing
To control the pulse widths for program and erase operations, the CMF EEPROM uses the system clock and the timing control in CMFCTL. The total pulse time is defined by the following pulse width equation: MPC555 MPC556 CDR MoneT FLASH EEPROM MOTOROLA USER’S MANUAL...
Page 680: System Clock Scaling
Never stop the U-bus clock or alter its frequency during a program or erase operation. Changing the clock frequency during a program or erase operation results in inaccurate pulse widths and variations in the charge pump output. This includes loss of system clock/PLL. MPC555 MPC556 CDR MoneT FLASH EEPROM MOTOROLA USER’S MANUAL...
Page 681: Exponential Clock Multiplier
19.7.6 A Technique to Determine SCLKR, CLKPE, and CLKPM The following example determines the values of the SCLKR, CLKPE, and CLKPM fields for a 25.6 µs program pulse, PE = 0, in a system with a 40 MHz system clock. MPC555 MPC556 CDR MoneT FLASH EEPROM MOTOROLA USER’S MANUAL...
Page 682: Starting And Ending A Program Or Erase Sequence
PROTECT[0:7], SCLKR[0:2], CLKPE[0:1], CLKPM[0:6], BLOCK[0:7], CSC and PE. The default reset state of SES is not configured for program or erase operation (SES = 0). MPC555 MPC556 CDR MoneT FLASH EEPROM MOTOROLA USER’S MANUAL...
Page 683: Controlling The Program/Erase Voltage
A soft reset or disabling the internal memory map clears EHV, terminating the high voltage pulse. 19.8 Censored and Non-Censored Accesses The MPC555 / MPC556 always operates in one of two modes: censored or uncen- sored. 19.8.1 Uncensored Mode Uncensored mode provides no censorship.
Page 684: Device Modes And Censorship Status
When booting from the internal flash, the default state is #8 unless BDM was entered, or a slave access to the MPC555 / MPC556 occurred. When any of these three con- ditions occur, then the state of CENSOR[0:1] determine whether the flash array can be accessed: 1.
Page 685: Setting And Clearing Censor
19-17. These two NVM bits are not part of the main flash array. The NVM fuse is not writable but instead may be set or cleared. The two NVM bits in the NVM fuse are programmed and erased simultaneously to change MPC555 MPC556 CDR MoneT FLASH EEPROM MOTOROLA USER’S MANUAL...
Page 686 7. Read the entire CMF array and the shadow information words. If any bit equals zero, go to step 4. ≠ 8. Read CENSOR[0:1]. If CENSOR[0:1] 0 go to step 4. 9. Write SES = 0 and CSC = 0. MPC555 MPC556 CDR MoneT FLASH EEPROM MOTOROLA USER’S MANUAL Rev. 15 October 2000...
Page 687: Switching The Cmf Eeprom Censorship
No Censorship Data CENSOR[0:1]=1 CENSOR[0:1]=2 Data Cleared Censorship Data Data CENSOR[0:1]=0 Unknown Figure 19-6 Censorship States and Transitions MPC555 MPC556 CDR MoneT FLASH EEPROM MOTOROLA USER’S MANUAL Rev. 15 October 2000 19-35 For More Information On This Product, Go to: www.freescale.com...
Page 688: Pin Descriptions
Pin Filter Pin Filter Output = 1 Output = 1 EPEE Pin = 0 @ ↑T2 Figure 19-7 EPEE Digital Filter and Latch MPC555 MPC556 CDR MoneT FLASH EEPROM MOTOROLA USER’S MANUAL Rev. 15 October 2000 19-36 For More Information On This Product,...
Page 689: Flash Program/Erase Voltage Conditioning
VPP transients. VPP must not rise to programming level while VDDL is below 1.0 volts, and must not fall below the minimum specified value while VDDL is applied. Figure 19-9 shows the VPP and VDDL operating envelope. MPC555 MPC556 CDR MoneT FLASH EEPROM MOTOROLA USER’S MANUAL Rev.
Page 690: Vpp And Vddl Power Switching
VDDL via Schottky diode D2, protecting VDDL from excessive reverse current. D2 also protects the FLASH from damage should the programming voltage go to zero. Programming power supply voltage must be adjusted to compensate for the forward- MPC555 MPC556 CDR MoneT FLASH EEPROM MOTOROLA USER’S MANUAL...
Page 691: Reset Operation
19.10 Reset Operation 19.10.1 Master Reset The MPC555 / MPC556 signals a master reset (both PORESET or HRESET) to the CMF EEPROM when a full reset is required. A master reset is the highest priority op- eration for the CMF EEPROM and will terminate all other operations. The CMF EE- PROM module uses master reset to initialize all register bits to their reset values.
Page 692: Emulation Operation
NOTE Although the program and erase operations can be suspended (EHV = 0) by disabling the internal memory, it is not recommended that pro- gram or erase be suspended in this manner. MPC555 MPC556 CDR MoneT FLASH EEPROM MOTOROLA USER’S MANUAL Rev.
Page 693: Features
SECTION 20 STATIC RANDOM ACCESS MEMORY (SRAM) The MPC555 / MPC556 contains two static random access memory (SRAM) modules: a 16-Kbyte module and a 10-Kbyte module. The SRAM modules provide the micro- controller unit (MCU) with fast (one cycle access), general-purpose memory. The SRAM can be read or written as either bytes, half words, or words.
Page 694: Programming Model
SRAM array. The reg- isters are located in the SRAM control register block, shown in Figure 20-2. See also Figure 1-3 for the entire MPC555 / MPC556 memory map. 0x38 0000 SRAMMCR_A 0x38 0004 SRAMTST_A...
Page 695: Sram Test Register (Sramtst)
TEA assertion. 20.3.2 SRAM Test Register (SRAMTST) SRAMTST — SRAM Test Register 0x38 0004, 0x38 000C The SRAM test register is used for factory testing only. MPC555 MPC556 STATIC RANDOM ACCESS MEMORY (SRAM) MOTOROLA USER’S MANUAL Rev.
Page 696 Freescale Semiconductor, Inc. MPC555 MPC556 STATIC RANDOM ACCESS MEMORY (SRAM) MOTOROLA USER’S MANUAL Rev. 15 October 2000 20-4 For More Information On This Product, Go to: www.freescale.com...
Page 697: Overview
The program instructions flow is visible on the external bus when the MPC555 / MPC556 is programmed to operate in serial mode and show all fetch cycles on the ex- ternal bus.
Page 698: Program Trace Cycle
In this way, the machine will always perform the additional external bus cycles and maintain exactly the same behavior both when VSYNC is asserted and when it is ne- gated. For more information refer to 21.7.6 I-Bus Support Control Register. MPC555 MPC556 DEVELOPMENT SUPPORT MOTOROLA USER’S MANUAL Rev.
Page 699: Instruction Queue Status Pins — Vf [0:2]
2. The sequential instructions listed here affect the machine in a manner similar to indirect branch instructions. Refer to 21.2.3 Sequential Instructions Marked as Indirect Branch. Table 21-2 shows VF[0:2] encodings for instruction queue flush information. MPC555 MPC556 DEVELOPMENT SUPPORT MOTOROLA USER’S MANUAL Rev. 15 October 2000...
Page 700: History Buffer Flushes Status Pins— Vfls [0..1]
VF pins report when the CPU returns to regular mode. If VSYNC was not changed while in debug mode. the first VF pins report will be of an indirect branch taken (VF = 101), suitable for the rfi instruction that is being issued. In both MPC555 MPC556 DEVELOPMENT SUPPORT MOTOROLA USER’S MANUAL...
Page 701: Sequential Instructions Marked As Indirect Branch
21.2.4.1 Synchronizing the Trace Window to the CPU Internal Events The assertion/negation of VSYNC is done using the serial interface implemented in the development port. In order to synchronize the assertion/negation of VSYNC to an in- MPC555 MPC556 DEVELOPMENT SUPPORT MOTOROLA USER’S MANUAL...
Page 702: Detecting The Trace Window Start Address
Assuming that VF1 and VF2 are the two first VF pins reports and T1 and T2 are the two addresses of the first two cycles marked with the program trace cycle attribute that were latched in the trace buffer, use the following table to calculate the trace window start address. MPC555 MPC556 DEVELOPMENT SUPPORT MOTOROLA USER’S MANUAL...
Page 703: Detecting The Assertion/Negation Of Vsync
External hardware can be added to eliminate all canceled instructions and report only on branches (taken and not taken), indirect flow change, and the num- ber of sequential instructions after the last flow change. MPC555 MPC556 DEVELOPMENT SUPPORT MOTOROLA USER’S MANUAL...
Page 704: Instruction Fetch Show Cycle Control
External breakpoints can be generated by any of the peripherals of the system, includ- ing those found on the MPC555 / MPC556 or externally, and also by an external de- velopment system. Peripherals found on the external bus use the serial interface of the development port to assert the external breakpoint.
Page 705 CPU is operating in the masked mode and the MSR[RI] bit is clear. The following figure illustrates the watchpoints and breakpoints support of the CPU. MPC555 MPC556 DEVELOPMENT SUPPORT MOTOROLA USER’S MANUAL...
Page 706: Watchpoints And Breakpoint Support In The Cpu
Freescale Semiconductor, Inc. Figure 21-1 Watchpoints and Breakpoint Support in the CPU MPC555 MPC556 DEVELOPMENT SUPPORT MOTOROLA USER’S MANUAL Rev. 15 October 2000 21-10 For More Information On This Product, Go to: www.freescale.com...
Page 707: Internal Watchpoints And Breakpoints
Key features of internal watchpoint and breakpoint support are: • Four I-address comparators (each supports equal, not equal, greater than, less than) • Two L-address comparators (each supports equal, not equal, greater than, less MPC555 MPC556 DEVELOPMENT SUPPORT MOTOROLA USER’S MANUAL Rev.
Page 708 • Load/store data compare is done on the load/store, AFTER swap in store access- es and BEFORE swap in load accesses (as the data appears on the bus). • Internal breakpoints may operate either in masked mode or in non-masked mode. MPC555 MPC556 DEVELOPMENT SUPPORT MOTOROLA USER’S MANUAL...
Page 709: Restrictions
Address range is supported only when aligned according to the access size. (See ex- amples) MPC555 MPC556 DEVELOPMENT SUPPORT MOTOROLA USER’S MANUAL Rev.
Page 710: Examples
(word, multiple), there might be some false detections. These can be ignored only by the software that handles the breakpoints. The following figure illustrates this partially supported scenario. MPC555 MPC556 DEVELOPMENT SUPPORT MOTOROLA USER’S MANUAL...
Page 711: Context Dependent Filter
MSRRI bit when operating in the masked mode), the first instruction will not cause an instruction breakpoint if the ignore first match (IFM) bit in the instruction support control register (ICTRL) is set (used for “continue”). MPC555 MPC556 DEVELOPMENT SUPPORT MOTOROLA USER’S MANUAL...
Page 712: Generating Six Compare Types
The instruction watchpoints and breakpoint are generated using these events and ac- cording to user programming. Note that using the OR option enables “out of range” de- tect. MPC555 MPC556 DEVELOPMENT SUPPORT MOTOROLA USER’S MANUAL...
Page 713: Load/Store Support
Figure 21-3 Instruction Support General Structure 21.3.2.1 Load/Store Support There are two load/store address comparators E, and F. Each compares the 32 ad- dress bits and the cycle’s attributes (read/write). The two least-significant bits are MPC555 MPC556 DEVELOPMENT SUPPORT MOTOROLA USER’S MANUAL...
Page 714 1. ‘&’ denotes a logical AND, ‘|’ denotes a logical OR The four load/store data events together with the match events of the load/store ad- dress comparators and the instruction watchpoints are used to generate the load/store watchpoints and breakpoint according to the users programming. MPC555 MPC556 DEVELOPMENT SUPPORT MOTOROLA USER’S MANUAL...
Page 715 Note that when programming the load/store watchpoints to ignore L-addr events and L-data events, it does not reduce the load/store watchpoints detection logic to be in- struction watchpoint detection logic since the instruction must be a load/store instruc- tion for the load/store watchpoint event to trigger. MPC555 MPC556 DEVELOPMENT SUPPORT MOTOROLA USER’S MANUAL...
Page 716: Load/Store Support General Structure
Events Generator Valid 3 Valid 2 Compare Size Valid 1 Valid 0 add(30:31) Figure 21-4 Load/Store Support General Structure MPC555 MPC556 DEVELOPMENT SUPPORT MOTOROLA USER’S MANUAL Rev. 15 October 2000 21-20 For More Information On This Product, Go to: www.freescale.com...
Page 717: Watchpoint Counters
21.4 Development System Interface When debugging an existing system, it is sometimes desirable to be able to do so with- out the need to insert any changes in the existing system. In some cases it is not de- MPC555 MPC556 DEVELOPMENT SUPPORT MOTOROLA USER’S MANUAL...
Page 718 When in debug mode an rfi instruction will return the machine to its regular work mode. The relationship between the debug mode logic to the rest of the CPU chip is shown in the following figure. MPC555 MPC556 DEVELOPMENT SUPPORT MOTOROLA USER’S MANUAL...
Page 719: Functional Diagram Of Mpc555 / Mpc556 Debug Mode Support
DSDO Shift Register DSDI Figure 21-5 Functional Diagram of MPC555 / MPC556 Debug Mode Support The development port provides a full duplex serial interface for communications be- tween the internal development support logic of the CPU and an external development tool.
Page 720: Debug Mode Support
An ex- ample is the ability of the development port to detect a debug mode access to a non existing memory space. The following figure illustrates the debug mode logic implemented in the CPU. MPC555 MPC556 DEVELOPMENT SUPPORT MOTOROLA USER’S MANUAL...
Page 721: Debug Mode Logic
Debug Enable Register (DER) reset freeze ECR_OR debug mode enable internal debug mode signal Figure 21-6 Debug Mode Logic MPC555 MPC556 DEVELOPMENT SUPPORT MOTOROLA USER’S MANUAL Rev. 15 October 2000 21-25 For More Information On This Product, Go to: www.freescale.com...
Page 722: Debug Mode Enable Vs. Debug Mode Disable
Since SRESET negation is done by an external pull up resistor any reference here to SRESET negation time refers to the time the MPC555 / MPC556 releases SRESET. If the actual negation is slow due to large resistor, set up time for the debug port signals should be set accordingly.
Page 723: Debug Mode Reset Configuration
Freescale Semiconductor, Inc. Figure 21-7 Debug Mode Reset Configuration When debug mode is disabled all events result in regular interrupt handling. MPC555 MPC556 DEVELOPMENT SUPPORT MOTOROLA USER’S MANUAL Rev. 15 October 2000 21-27 For More Information On This Product, Go to: www.freescale.com...
Page 724 Useful in some catastrophic events like an endless loop when MSRRI = 0. As a result of this event the machine may enter a non-restartable state, for more information re- fer to 3.15.4 Interrupts. MPC555 MPC556 DEVELOPMENT SUPPORT MOTOROLA USER’S MANUAL Rev.
Page 725: The Check Stop State And Debug Mode
21.4.1.4 Saving Machine State upon Entering Debug Mode If entering debug mode was as a result of any load/store type exception, and therefore the DAR (data address register) and DSISR (data storage interrupt status register) MPC555 MPC556 DEVELOPMENT SUPPORT MOTOROLA USER’S MANUAL...
Page 726: Running In Debug Mode
The development system may monitor the freeze status to make sure the MPC555 / MPC556 is out of debug mode. It is the responsibility of the software to read the exception cause register (ECR) before...
Page 727: Development Port
When driven asynchronous (synchronous) with the system clock, the data presented to DSDI must be stable a setup time before the rising edge of DSCK (CLKOUT) and a hold time after the rising edge of DSCK (CLKOUT). MPC555 MPC556 DEVELOPMENT SUPPORT MOTOROLA USER’S MANUAL...
Page 728: Development Serial Data Out
The freeze indication means that the processor is in debug mode (i.e., normal proces- sor execution of user code is frozen). On the MPC555 / MPC556, the freeze state can be indicated by three different pins. The FRZ signal is generated synchronously with the system clock.
Page 729: Development Port Shift Register
CPU is fetching instructions or reading or writing data. If what the CPU is expecting and what the register receives from the serial port do not match (instruction instead of data) the mismatch is used to signal a sequence error to the external devel- opment tool. MPC555 MPC556 DEVELOPMENT SUPPORT MOTOROLA USER’S MANUAL...
Page 730: Development Port Serial Communications — Clock Mode Selection
The first method allows the transmission to occur without being externally synchronized with CLKOUT, in this mode a serial clock DSCK must be supplied to the MPC555 / MPC556. The other com- munication method requires a data to be externally synchronized with CLKOUT.
Page 731: Asynchronous Clock Serial Communications
Freescale Semiconductor, Inc. Figure 21-8 Asynchronous Clock Serial Communications MPC555 MPC556 DEVELOPMENT SUPPORT MOTOROLA USER’S MANUAL Rev. 15 October 2000 21-35 For More Information On This Product, Go to: www.freescale.com...
Page 732: Synchronous Self Clock Serial Communication
Freescale Semiconductor, Inc. Figure 21-9 Synchronous Self Clock Serial Communication MPC555 MPC556 DEVELOPMENT SUPPORT MOTOROLA USER’S MANUAL Rev. 15 October 2000 21-36 For More Information On This Product, Go to: www.freescale.com...
Page 733: Enabling Clock Mode Following Reset
Freescale Semiconductor, Inc. Figure 21-10 Enabling Clock Mode Following Reset MPC555 MPC556 DEVELOPMENT SUPPORT MOTOROLA USER’S MANUAL Rev. 15 October 2000 21-37 For More Information On This Product, Go to: www.freescale.com...
Page 734: Development Port Serial Communications — Trap Enable Mode
Assert Non Maskable breakpoint. The watchpoint trap enables and VSYNC functions are described in section 21.3 Watchpoints and Breakpoints Support and section 21.2 Program Flow Tracking. MPC555 MPC556 DEVELOPMENT SUPPORT MOTOROLA USER’S MANUAL Rev. 15 October 2000 21-38 For More Information On This Product,...
Page 735: Serial Data Out Of Development Port — Trap Enable Mode
After detecting this ready status the external de- velopment tool begins the transmission to the development port with a start bit (logic high) on the DSDI pin. MPC555 MPC556 DEVELOPMENT SUPPORT MOTOROLA USER’S MANUAL...
Page 736: Serial Data Into Development Port
The NOP function provides a null operation for use when there is data or a response to be shifted out of the data register and the appropriate next instruction or command will be determined by the value of the response or data shifted out. MPC555 MPC556 DEVELOPMENT SUPPORT MOTOROLA USER’S MANUAL...
Page 737: Serial Data Out Of Development Port
The download procedure is used to download a block of data from the debug tool into system memory. This procedure can be accomplished by repeating the following se- quence of transactions from the development tool to the debug port for the number of data words to be down loaded: MPC555 MPC556 DEVELOPMENT SUPPORT MOTOROLA USER’S MANUAL...
Page 738: Download Procedure Code Example
Internal Activity Figure 21-12 Slow Download Procedure Loop External DATA Transaction Internal Activity Figure 21-13 Fast Download Procedure Loop MPC555 MPC556 DEVELOPMENT SUPPORT MOTOROLA USER’S MANUAL Rev. 15 October 2000 21-42 For More Information On This Product, Go to: www.freescale.com...
Page 739: Software Monitor Debugger Support
21.7 Development Support Registers Table 21-14 lists the registers used for development support. The registers are ac- cessed with the mtspr and mfspr instructions. MPC555 MPC556 DEVELOPMENT SUPPORT MOTOROLA USER’S MANUAL Rev. 15 October 2000...
Page 740: Register Protection
21.7.1 Register Protection Table 21-15 Table 21-16 summarize protection features of development support registers during read and write accesses, respectively. MPC555 MPC556 DEVELOPMENT SUPPORT MOTOROLA USER’S MANUAL Rev. 15 October 2000 21-44 For More Information On This Product,...
Page 741: Comparator A–D Value Registers (Cmpa–Cmpd)
RESET: UNAFFECTED Table 21-17 CMPA-CMPD Bit Descriptions Bits Mnemonic Description 0:29 CMPAD Address bits to be compared 30:31 — Reserved MPC555 MPC556 DEVELOPMENT SUPPORT MOTOROLA USER’S MANUAL Rev. 15 October 2000 21-45 For More Information On This Product, Go to: www.freescale.com...
Page 742: Comparator E–F Value Registers
Table 21-20 CMPG-CMPH Bit Descriptions Bits Mnemonic Description 0:31 CMPGH Data bits to be compared These registers are unaffected by reset. MPC555 MPC556 DEVELOPMENT SUPPORT MOTOROLA USER’S MANUAL Rev. 15 October 2000 21-46 For More Information On This Product, Go to: www.freescale.com...
Page 743: I-Bus Support Control Register
If the processor aborts a fetch of the target of a direct branch (due to an exception), the target is not always visible on the external pins. Program trace is not affected by this phenomenon. MPC555 MPC556 DEVELOPMENT SUPPORT MOTOROLA USER’S MANUAL...
Page 744 29:31 ISCT_SER RCPU serialize control NOTE: Changing the instruction show cycle pro- gramming starts to take effect only from the sec- ond instruction after the actual mtspr to ICTRL. MPC555 MPC556 DEVELOPMENT SUPPORT MOTOROLA USER’S MANUAL Rev. 15 October 2000...
Page 745: L-Bus Support Control Register 1
21.7.7 L-Bus Support Control Register 1 LCTRL1 — L-Bus Support Control Register 1 SPR 156 CRWE CRWF RESET: SUSG SUSH CGBMSK CHBMSK UNUSED RESET: MPC555 MPC556 DEVELOPMENT SUPPORT MOTOROLA USER’S MANUAL Rev. 15 October 2000 21-49 For More Information On This Product, Go to: www.freescale.com...
Page 746: L-Bus Support Control Register 2
LW0LD LW1EN LW1IA LW1LA IADC LADC LDDC IADC RESET: DLW0 DLW1 SLW0 SLW1 LW1LD RESERVED LADC LDDC NOMSK RESET: MPC555 MPC556 DEVELOPMENT SUPPORT MOTOROLA USER’S MANUAL Rev. 15 October 2000 21-50 For More Information On This Product, Go to: www.freescale.com...
Page 747 Internal breakpoints non-mask only when MSR[RI]=1 (reset value) BRKNOMSK 1 = non-masked mode; breakpoints are always recognized 21:27 — Reserved — MPC555 MPC556 DEVELOPMENT SUPPORT MOTOROLA USER’S MANUAL Rev. 15 October 2000 21-51 For More Information On This Product, Go to: www.freescale.com...
Page 748: Breakpoint Counter A Value And Control Register
00 = not active (reset value) 01 = I-bus first watchpoint 30:31 CNTC 10 =L-bus first watchpoint 11 = Reserved COUNTA[16:31] are cleared following reset; COUNTA[0:15] are unaffected by reset. MPC555 MPC556 DEVELOPMENT SUPPORT MOTOROLA USER’S MANUAL Rev. 15 October 2000 21-52 For More Information On This Product, Go to: www.freescale.com...
Page 749: Breakpoint Counter B Value And Control Register
Attempts to write to this register are ignored. When the hardware sets a bit in this register, debug mode is entered only if debug mode is enabled and the corresponding mask bit in the DER is set. All bits are cleared to zero following reset. MPC555 MPC556 DEVELOPMENT SUPPORT MOTOROLA USER’S MANUAL...
Page 750 This bit is set as a result of an data protection error. Results in debug mode entry if debug mode is enabled and the corresponding enable bit is set. 22:27 — Reserved MPC555 MPC556 DEVELOPMENT SUPPORT MOTOROLA USER’S MANUAL Rev. 15 October 2000...
Page 751: Debug Enable Register (Der)
1 = Debug mode entry enabled (reset value) Machine check exception enable bit MCEE 0 = Debug mode entry disabled (reset value) 1 = Debug mode entry enabled — Reserved MPC555 MPC556 DEVELOPMENT SUPPORT MOTOROLA USER’S MANUAL Rev. 15 October 2000 21-55 For More Information On This Product, Go to: www.freescale.com...
Page 752 0 = Debug mode entry disabled 1 = Debug mode entry enabled (reset value) Development port interrupt enable bit DPIE 0 = Debug mode entry disabled 1 = Debug mode entry enabled (reset value) MPC555 MPC556 DEVELOPMENT SUPPORT MOTOROLA USER’S MANUAL Rev. 15 October 2000...
Page 753: Development Port Data Register (Dpdr)
An ac- cess to this register is initiated using mtspr and mfspr (SPR 630) and implemented using a special bus cycle on the internal bus. MPC555 MPC556 DEVELOPMENT SUPPORT MOTOROLA USER’S MANUAL...
Page 754 Freescale Semiconductor, Inc. MPC555 MPC556 DEVELOPMENT SUPPORT MOTOROLA USER’S MANUAL Rev. 15 October 2000 21-58 For More Information On This Product, Go to: www.freescale.com...
Page 755: Jtag Interface Block Diagram
Problems associated with testing high-density circuit boards have led to development of this standard under the sponsorship of the Test Technology Commit- tee of IEEE and the Joint Test Action Group (JTAG). The MPC555 / MPC556 supports circuit-board test strategies based on this standard.
Page 756: Jtag Signal Descriptions
Figure 22-2 Test Logic Block Diagram 22.2 JTAG Signal Descriptions The MPC555 / MPC556 has five dedicated JTAG pins, which are described in Table 22-1. The TDI and TDO scan ports are used to scan instructions as well as data into the various scan registers for JTAG operations.
Page 757: Operating Frequency
IR controller states. During these controller states, TDO is updated on the falling edge of TCK. The TAP controller states are designed to meet the IEEE 1149.1 standard. Refer to Figure 22-3. MPC555 MPC556 IEEE 1149.1-COMPLIANT INTERFACE (JTAG) MOTOROLA USER’S MANUAL Rev.
Page 758: Instruction Register
(HI-Z) provides the capability for disabling all device output driv- ers. The MPC555 / MPC556 includes a 4-bit instruction register without parity consisting of a shift register with four parallel outputs. Data is transferred from the shift register to the parallel outputs during the update-IR controller state.
Page 759: Extest
22.5.1 EXTEST The external test (EXTEST) instruction selects the 346-bit boundary scan register. EX- TEST also asserts internal reset for the MPC555 / MPC556 system logic to force a pre- dictable beginning internal state while performing external boundary scan operations.
Page 760: Clamp
22.7 Low-Power Stop Mode The MPC555 / MPC556 features a low-power stop mode. The interaction of the scan chain interface with low-power stop mode is as follows: 1. The TAP controller must be in the test-logic-reset state to either enter or remain in the low-power stop mode.
Page 761: Non-Ieee 1149.1-1990 Operation
TRST to the negated state (“1” value) following PORESET. 22.9 Boundary Scan Register The MPC555 / MPC556 scan chain implementation has a 346-bit boundary scan reg- ister. This register contains bits for all device signal and clock pins and associated con- trol signals.
Page 762: Output Pin Cell (O.pin)
DATA TO SYSTEM LOGIC CLOCK DR FROM SHIFT DR LAST CELL Figure 22-6 Observe-Only Input Pin Cell (I.Obs) MPC555 MPC556 IEEE 1149.1-COMPLIANT INTERFACE (JTAG) MOTOROLA USER’S MANUAL Rev. 15 October 2000 22-8 For More Information On This Product, Go to: www.freescale.com...
Page 763: Output Control Cell (Io.ctl)
The key to using the boundary scan register is knowing the boundary scan bit order and the pins that are associated with them. Below in Table 22-3 is the bit order starting MPC555 MPC556 IEEE 1149.1-COMPLIANT INTERFACE (JTAG) MOTOROLA USER’S MANUAL Rev.
Page 764 The shift register cell nearest TDI (i.e., first to be shifted in) is defined as bit 1; the last bit to be shifted in is 345. The second column references one of the three MPC555 / MPC556 cell types depicted Figure 22-5...
Page 765 — — IO.PIN a_tpuch3 g304.ctl IO.ctl g304.ctl — — IO.PIN a_tpuch4 g305.ctl IO.ctl g305.ctl — — MPC555 MPC556 IEEE 1149.1-COMPLIANT INTERFACE (JTAG) MOTOROLA USER’S MANUAL Rev. 15 October 2000 22-11 For More Information On This Product, Go to: www.freescale.com...
Page 766 — i.obs a_an48_pqb4 — i.obs a_an49_pqb5 — IO.PIN a_an50_pqb6 g333.ctl IO.ctl g333.ctl — — IO.PIN a_an51_pqb7 g334.ctl MPC555 MPC556 IEEE 1149.1-COMPLIANT INTERFACE (JTAG) MOTOROLA USER’S MANUAL Rev. 15 October 2000 22-12 For More Information On This Product, Go to: www.freescale.com...
Page 767 — — IO.PIN b_an52_ma0_pqa0 g351.ctl IO.ctl g351.ctl — — IO.PIN b_an53_ma1_pqa1 g352.ctl IO.ctl g352.ctl — — MPC555 MPC556 IEEE 1149.1-COMPLIANT INTERFACE (JTAG) MOTOROLA USER’S MANUAL Rev. 15 October 2000 22-13 For More Information On This Product, Go to: www.freescale.com...
Page 768 IO.PIN mda28 g371.ctl IO.ctl g371.ctl — — IO.PIN mda29 g372.ctl IO.ctl g372.ctl — — IO.PIN mda30 g403.ctl MPC555 MPC556 IEEE 1149.1-COMPLIANT INTERFACE (JTAG) MOTOROLA USER’S MANUAL Rev. 15 October 2000 22-14 For More Information On This Product, Go to: www.freescale.com...
Page 769 — — IO.PIN mpio32b9 g417.ctl IO.ctl g417.ctl — — IO.PIN mpio32b10 g418.ctl IO.ctl g418.ctl — — MPC555 MPC556 IEEE 1149.1-COMPLIANT INTERFACE (JTAG) MOTOROLA USER’S MANUAL Rev. 15 October 2000 22-15 For More Information On This Product, Go to: www.freescale.com...
Page 770 IO.PIN pcs2_qgpio2 g437.ctl IO.ctl g437.ctl — — IO.PIN pcs3_qgpio3 g438.ctl IO.ctl g438.ctl — — IO.PIN miso_qgpio4 g439.ctl MPC555 MPC556 IEEE 1149.1-COMPLIANT INTERFACE (JTAG) MOTOROLA USER’S MANUAL Rev. 15 October 2000 22-16 For More Information On This Product, Go to: www.freescale.com...
Page 771 IO.ctl g503.ctl — — IO.PIN data_sgpiod[16] g112.ctl IO.ctl g112.ctl — — IO.PIN data_sgpiod[17] g112.ctl IO.PIN data_sgpiod[18] g112.ctl MPC555 MPC556 IEEE 1149.1-COMPLIANT INTERFACE (JTAG) MOTOROLA USER’S MANUAL Rev. 15 October 2000 22-17 For More Information On This Product, Go to: www.freescale.com...
Page 772 IO.PIN data_sgpiod[28] g534.ctl IO.ctl g534.ctl — — IO.PIN data_sgpiod[29] g535.ctl IO.ctl g535.ctl — — IO.PIN data_sgpiod[2] g110.ctl MPC555 MPC556 IEEE 1149.1-COMPLIANT INTERFACE (JTAG) MOTOROLA USER’S MANUAL Rev. 15 October 2000 22-18 For More Information On This Product, Go to: www.freescale.com...
Page 773 IO.PIN addr_sgpioa[17] g101.ctl IO.PIN addr_sgpioa[16] g101.ctl IO.ctl g101.ctl — — IO.PIN addr_sgpioa[10] g100.ctl IO.PIN addr_sgpioa[15] g100.ctl MPC555 MPC556 IEEE 1149.1-COMPLIANT INTERFACE (JTAG) MOTOROLA USER’S MANUAL Rev. 15 October 2000 22-19 For More Information On This Product, Go to: www.freescale.com...
Page 774 — o.pin we_b_at[1] — o.pin we_b_at[0] — IO.PIN br_b_vf1_iwp2 g227.ctl IO.ctl g227.ctl — — IO.PIN bg_b_vf0_lwp1 g228.ctl MPC555 MPC556 IEEE 1149.1-COMPLIANT INTERFACE (JTAG) MOTOROLA USER’S MANUAL Rev. 15 October 2000 22-20 For More Information On This Product, Go to: www.freescale.com...
Page 775 IO.ctl g237.ctl — — o.pin iwp0_vfls0 — o.pin iwp1_vfls1 — IO.PIN sgpioc6_frz_ptr_b g240.ctl IO.ctl g240.ctl — — MPC555 MPC556 IEEE 1149.1-COMPLIANT INTERFACE (JTAG) MOTOROLA USER’S MANUAL Rev. 15 October 2000 22-21 For More Information On This Product, Go to: www.freescale.com...
Page 776 Freescale Semiconductor, Inc. MPC555 MPC556 IEEE 1149.1-COMPLIANT INTERFACE (JTAG) MOTOROLA USER’S MANUAL Rev. 15 October 2000 22-22 For More Information On This Product, Go to: www.freescale.com...
Page 777 Table A-12 UIMB (U-Bus to IMB3 Bus Interface) Table A-13 SRAM (Static RAM Access Memory) Table A-14 SRAM (Static RAM Access Memory) Array MPC555 / MPC556 MPC555 / MPC556 INTERNAL MEMORY MAP MOTOROLA USER’S MANUAL Rev. 15 October 2000 For More Information On This Product,...
Page 778 Breakpoint Counter A Value and Control Reg- SPR 150 COUNTA ister Table 21-25 for bit descriptions. MPC555 / MPC556 MPC555 / MPC556 INTERNAL MEMORY MAP MOTOROLA USER’S MANUAL Rev. 15 October 2000 For More Information On This Product, Go to: www.freescale.com...
Page 779 Development Port Data Register. Internal Memory Mapping Register. SPR 638 IMMR Table 6-11 for bit descriptions. MPC555 / MPC556 MPC555 / MPC556 INTERNAL MEMORY MAP MOTOROLA USER’S MANUAL Rev. 15 October 2000 For More Information On This Product, Go to: www.freescale.com...
Page 780 — 0x03 FFFF 0x04 0000 – CMF_B Flash Array 8, 16, 32 — 0x06 FFFF MPC555 / MPC556 MPC555 / MPC556 INTERNAL MEMORY MAP MOTOROLA USER’S MANUAL Rev. 15 October 2000 For More Information On This Product, Go to: www.freescale.com...
Page 781 Table 10-8 for bit descriptions. Base Register 3. 0x2F C118 Table 10-7 for bit descriptions. MPC555 / MPC556 MPC555 / MPC556 INTERNAL MEMORY MAP MOTOROLA USER’S MANUAL Rev. 15 October 2000 For More Information On This Product, Go to: www.freescale.com...
Page 782 Clocks and Reset System Clock Control Register. 0x2F C280 SCCR Table 8-9 for bit descriptions. MPC555 / MPC556 MPC555 / MPC556 INTERNAL MEMORY MAP MOTOROLA USER’S MANUAL Rev. 15 October 2000 For More Information On This Product, Go to: www.freescale.com...
Page 783 RSRK Table 8-8 for bit descriptions. 0x2F C38C – — Reserved — — 0x2F C3FC MPC555 / MPC556 MPC555 / MPC556 INTERNAL MEMORY MAP MOTOROLA USER’S MANUAL Rev. 15 October 2000 For More Information On This Product, Go to: www.freescale.com...
Page 784 NOTES: 1. Bit 3 (FIC) is write-once. Bit 0 (LOCK) is write-once unless in freeze or test mode. MPC555 / MPC556 MPC555 / MPC556 INTERNAL MEMORY MAP MOTOROLA USER’S MANUAL Rev. 15 October 2000 For More Information On This Product,...
Page 785 0x30 37FF NOTES: 1. Access to the DPTRAM array through the IMB3 bus is disabled once bit 5 (EMU) of either TPUMCR is set. MPC555 / MPC556 MPC555 / MPC556 INTERNAL MEMORY MAP MOTOROLA USER’S MANUAL Rev. 15 October 2000 For More Information On This Product, Go to: www.freescale.com...
Page 786 TPU_A Module Configuration Register 2. 0x30 4028 TPUMCR2_A S, M Table 17-17 for bit descriptions. MPC555 / MPC556 MPC555 / MPC556 INTERNAL MEMORY MAP MOTOROLA USER’S MANUAL Rev. 15 October 2000 A-10 For More Information On This Product, Go to: www.freescale.com...
Page 787 TPU3_B Interrupt Configuration Register S, M 0x30 440A CIER_B TPU3_B Channel Interrupt Enable Register S, M MPC555 / MPC556 MPC555 / MPC556 INTERNAL MEMORY MAP MOTOROLA USER’S MANUAL Rev. 15 October 2000 A-11 For More Information On This Product, Go to: www.freescale.com...
Page 788 0x30 459E 0x30 45A0 – — TPU_B Channel 10 Parameter Registers 16, 32 0x30 45AE MPC555 / MPC556 MPC555 / MPC556 INTERNAL MEMORY MAP MOTOROLA USER’S MANUAL Rev. 15 October 2000 A-12 For More Information On This Product, Go to: www.freescale.com...
Page 789 0x30 4A00 – Conversion Command Word Table. CCW_A 0x30 4A7E Table 13-19 for bit descriptions. MPC555 / MPC556 MPC555 / MPC556 INTERNAL MEMORY MAP MOTOROLA USER’S MANUAL Rev. 15 October 2000 A-13 For More Information On This Product, Go to: www.freescale.com...
Page 790 0x30 4FFE Left-Justified, Unsigned Result Register. NOTES: 1. Bit 3 (SSEx) is readable in test mode only. MPC555 / MPC556 MPC555 / MPC556 INTERNAL MEMORY MAP MOTOROLA USER’S MANUAL Rev. 15 October 2000 A-14 For More Information On This Product,...
Page 791 Receive Queue Locations 0x30 506A 0x30 506C – — — Reserved — — 0x30 5013F MPC555 / MPC556 MPC555 / MPC556 INTERNAL MEMORY MAP MOTOROLA USER’S MANUAL Rev. 15 October 2000 A-15 For More Information On This Product, Go to: www.freescale.com...
Page 792 MPWMSM3 Count Register. 0x30 601C MPWMSMCNTR Table 15-22 for bit descriptions. MPC555 / MPC556 MPC555 / MPC556 INTERNAL MEMORY MAP MOTOROLA USER’S MANUAL Rev. 15 October 2000 A-16 For More Information On This Product, Go to: www.freescale.com...
Page 793 MDASM13 Status/Control Register Duplicat- 0x30 606C MDASMSCRD 15.11.1.3 MDASM Status/Control Reg- ister (Duplicated) for bit descriptions. MPC555 / MPC556 MPC555 / MPC556 INTERNAL MEMORY MAP MOTOROLA USER’S MANUAL Rev. 15 October 2000 A-17 For More Information On This Product, Go to: www.freescale.com...
Page 794 MPWMSM17 Status/Control Register. 0x30 608E MPWMSMSCR Table 15-23 for bit descriptions. MPC555 / MPC556 MPC555 / MPC556 INTERNAL MEMORY MAP MOTOROLA USER’S MANUAL Rev. 15 October 2000 A-18 For More Information On This Product, Go to: www.freescale.com...
Page 795 MDASM28 Data B Register. 0x30 60E2 MDASMBR 15.11.1.2 MDASM Data B Register (MDASMBR) for bit descriptions. MPC555 / MPC556 MPC555 / MPC556 INTERNAL MEMORY MAP MOTOROLA USER’S MANUAL Rev. 15 October 2000 A-19 For More Information On This Product, Go to: www.freescale.com...
Page 796 MPIOSM Data Direction Register. 0x30 6102 MPIOSMDDR Table 15-27 for bit descriptions. MPC555 / MPC556 MPC555 / MPC556 INTERNAL MEMORY MAP MOTOROLA USER’S MANUAL Rev. 15 October 2000 A-20 For More Information On This Product, Go to: www.freescale.com...
Page 797 MIOS1LVL1 Table 15-8 for bit descriptions. NOTES: 1. Bit 0 (TEST) is reserved for factory testing. MPC555 / MPC556 MPC555 / MPC556 INTERNAL MEMORY MAP MOTOROLA USER’S MANUAL Rev. 15 October 2000 A-21 For More Information On This Product, Go to: www.freescale.com...
Page 798 TouCAN_A Receive Error Counter/ RXECTR_A/ 0x30 70A6 TouCAN_A Transmit Error Counter. TXECTR_A Table 16-26 for bit descriptions. MPC555 / MPC556 MPC555 / MPC556 INTERNAL MEMORY MAP MOTOROLA USER’S MANUAL Rev. 15 October 2000 A-22 For More Information On This Product, Go to: www.freescale.com...
Page 799 0x3071F0 — MBUFF15_A Figure 16-3 Figure 16-4 for mes- — 0x3071FF sage buffer definitions. MPC555 / MPC556 MPC555 / MPC556 INTERNAL MEMORY MAP MOTOROLA USER’S MANUAL Rev. 15 October 2000 A-23 For More Information On This Product, Go to: www.freescale.com...
Page 800 TouCAN_B Message Buffer 8. — 0x30758F 0x307590 — MBUFF9_B TouCAN_B Message Buffer 9. — 0x30759F MPC555 / MPC556 MPC555 / MPC556 INTERNAL MEMORY MAP MOTOROLA USER’S MANUAL Rev. 15 October 2000 A-24 For More Information On This Product, Go to: www.freescale.com...
Page 801 SRAMTST_B SRAM_B Test Register. NOTES: 1. Bit 0 (LCK) locks the register (write-protected except in test mode) and is write once. MPC555 / MPC556 MPC555 / MPC556 INTERNAL MEMORY MAP MOTOROLA USER’S MANUAL Rev. 15 October 2000 A-25 For More Information On This Product,...
Page 802 U, S SRAM_B RAM Array (16 K Bytes) 8, 16, 32 — 0x3F FFFF MPC555 / MPC556 MPC555 / MPC556 INTERNAL MEMORY MAP MOTOROLA USER’S MANUAL Rev. 15 October 2000 A-26 For More Information On This Product, Go to: www.freescale.com...
Page 803 COUNTB (breakpoint counter B value and control register) 21-53 CPR0 (TPU3 channel priority register 0) 17-18 CPR1 (TPU3 channel priority register 1) 17-18 CR (condition register) 3-16 MPC555 / MPC556 REGISTER GENERAL INDEX MOTOROLA USER’S MANUAL Rev. 15 October 2000 For More Information On This Product, Go to: www.freescale.com...
Page 804 IMASK (interrupt mask register) 16-32 IMMR (internal memory mapping register) 6-21 Internal memory map register 6-21 –K– Keep alive power registers lock mechanism 8-23 MPC555 / MPC556 REGISTER GENERAL INDEX MOTOROLA USER’S MANUAL Rev. 15 October 2000 For More Information On This Product,...
Page 805 MIOS1ER1 (interrupt enable register) 15-37 MIOS1LVL0 (MIOS1 interrupt level register 0) 15-11 MIOS1LVL1 (MIOS1 interrupt level 1 register) 15-11 MIOS1MCR (MIOS1 module configuration register) 15-9 MIOS1RPR0 (MIRSM0 request pending register) 15-35 MPC555 / MPC556 REGISTER GENERAL INDEX MOTOROLA USER’S MANUAL Rev. 15 October 2000 For More Information On This Product, Go to: www.freescale.com...
Page 806 PLPRCR (PLL, low power, and reset control register) 8-33 PORTQA (port QA data register) 13-34 PORTQB (port QB data register) 13-34 PORTQS (port QS data register) 14-11 MPC555 / MPC556 REGISTER GENERAL INDEX MOTOROLA USER’S MANUAL Rev. 15 October 2000 For More Information On This Product, Go to: www.freescale.com...
Page 807 3-27 condition register (CR) 3-15 condition register CR0 field definition 3-16 condition register CR1 field definition 3-16 condition register crn field - compare instruction 3-17 MPC555 / MPC556 REGISTER GENERAL INDEX MOTOROLA USER’S MANUAL Rev. 15 October 2000 For More Information On This Product, Go to: www.freescale.com...
Page 808 (SIVEC) 6-25 module configuration register (SIUMCR) 6-18 SIUMCR (SIU module configuration register) 6-18 SIVEC (SIU interrupt vector) 6-25 Software service register (SWSR) 6-26 MPC555 / MPC556 REGISTER GENERAL INDEX MOTOROLA USER’S MANUAL Rev. 15 October 2000 For More Information On This Product,...
Page 809 (HSSRx) 17-17 interrupt configuration register (TICR) 17-14 link register (LR) 17-19 module configuration register (TPUMCR) 17-10 module configuration register 2 (TPUMCR2) 17-20 MPC555 / MPC556 REGISTER GENERAL INDEX MOTOROLA USER’S MANUAL Rev. 15 October 2000 For More Information On This Product,...
Page 810 UMCR (UIMB module configuration register) 12-7 –V– VDDSRM sensor register (VSRMSR) 8-36 VSRMSR (VDDSRM control register) 8-36 –X– XER (integer exception register) 3-17 MPC555 / MPC556 REGISTER GENERAL INDEX MOTOROLA USER’S MANUAL Rev. 15 October 2000 For More Information On This Product, Go to: www.freescale.com...
Page 811 DSSR (TPU3 development support status register) 17-14 –E– ECR (exception cause register) 21-54 EMCR (external master control register) 6-22 ESTAT (error and status register) 16-30 MPC555 / MPC556 REGISTER DIAGRAM INDEX MOTOROLA USER’S MANUAL Rev. 15 October 2000 For More Information On This Product,...
Page 812 MMCSMML (MMCSM modulus latch register) 15-16 MMCSMSCR (MMCSM status/control register) 15-17 MMCSMSCRD (MMCSM status/control register - duplicated) 15-17 MPIOSMDDR (MPIOSM data direction register) 15-31 MPIOSMDR (MPIOSM data register) 15-31 MPC555 / MPC556 REGISTER DIAGRAM INDEX MOTOROLA USER’S MANUAL Rev. 15 October 2000 For More Information On This Product, Go to: www.freescale.com...
Page 813 SGPIOCR (SGPIO control register) 6-35 SGPIODT1 (SGPIO data register 1) 6-34 SGPIODT2 (SGPIO data register 2) 6-34 SIEL (SIU interrupt edge level register) 6-25 SIMASK (SIU interrupt mask register) 6-24 MPC555 / MPC556 REGISTER DIAGRAM INDEX MOTOROLA USER’S MANUAL Rev. 15 October 2000 For More Information On This Product, Go to: www.freescale.com...
Page 814 UIPEND (UIMB pending interrupt reqiuest register) 12-8 UMCR (UIMB module configuration register) 12-7 –V– VSRMSR (VDDSRM control register) 8-36 –X– XER (integer exception register) 3-17 MPC555 / MPC556 REGISTER DIAGRAM INDEX MOTOROLA USER’S MANUAL Rev. 15 October 2000 For More Information On This Product,...
Page 815: D.1 Overview
The TPU3 contains four Kbytes of microcode ROM. This appendix defines the func- tions that are in the standard ROM on the MPC555 / MPC556. The TPU3 can have up to eight Kbytes of memory and a maximum of four entry tables (see Figure D-1).
Page 816 Synchronized Pulse Width Modulation SIOP Serial Input/output Port The functions in the entry table in bank one are listed in Table D-2. MPC555 / MPC556 TPU ROM FUNCTIONS MOTOROLA USER’S MANUAL Rev. 15 October 2000 For More Information On This Product,...
Page 817 TPU3 will be reset and the entry table in Bank 0 will be se- lected by default. To select the Bank 0 entry table, write 0b00 to the ETBANK field in MPC555 / MPC556 TPU ROM FUNCTIONS MOTOROLA USER’S MANUAL...
Page 818: D.2 Programmable Time Accumulator (Pta)
Motorola TPU Progamming Note Programmable Time Accumulator TPU Function (PTA), (TPUPN06/D). Figure D-2 shows all of the host interface areas for the PTA function. MPC555 / MPC556 TPU ROM FUNCTIONS MOTOROLA USER’S MANUAL Rev. 15 October 2000 For More Information On This Product,...
Page 819: D-2 Pta Parameters
W = Channel Number YY = 41 for TPU_A and 44 for TPU_B = Written By TPU = Unused Parameters Figure D-2 PTA Parameters MPC555 / MPC556 TPU ROM FUNCTIONS MOTOROLA USER’S MANUAL Rev. 15 October 2000 For More Information On This Product,...
Page 820: D.3 Queued Output Match Tpu Function (Qom)
Rising Edge at Match Reference for First Match Immediate TCR Value Last Event Time Value Pointed to by REF_ADDR Last Event Time MPC555 / MPC556 TPU ROM FUNCTIONS MOTOROLA USER’S MANUAL Rev. 15 October 2000 For More Information On This Product,...
Page 821: D-3 Qom Parameters
W = Channel Number YY = 41 for TPU_A and 44 for TPU_B = Written By TPU = Unused Parameters Figure D-3 QOM Parameters MPC555 / MPC556 TPU ROM FUNCTIONS MOTOROLA USER’S MANUAL Rev. 15 October 2000 For More Information On This Product,...
Page 822: D.4 Table Stepper Motor (Tsm)
Table Stepper Motor TPU Function (TSM), (TPUPN04/D). Figure D-4 Figure D-5 show all of the host interface areas for the TSM function when operating in master and slave mode, respectively. MPC555 / MPC556 TPU ROM FUNCTIONS MOTOROLA USER’S MANUAL Rev. 15 October 2000 For More Information On This Product, Go to: www.freescale.com...
Page 823: D-4 Tsm Parameters — Master Mode
YY = 41 for TPU_A and 44 for TPU_B = Written By TPU = Unused Parameters Figure D-4 TSM Parameters — Master Mode MPC555 / MPC556 TPU ROM FUNCTIONS MOTOROLA USER’S MANUAL Rev. 15 October 2000 For More Information On This Product,...
Page 824: D-5 Tsm Parameters — Slave Mode
W = Channel Number YY = 41 for TPU_A and 44 for TPU_B = Written By TPU = Unused Parameters Figure D-5 TSM Parameters — Slave Mode MPC555 / MPC556 TPU ROM FUNCTIONS MOTOROLA USER’S MANUAL Rev. 15 October 2000 D-10 For More Information On This Product, Go to: www.freescale.com...
Page 825: D.5 Frequency Measurement (Fqm)
PTA.See Motorola TPU Progamming Note Frequency Measurement TPU Function (FQM), (TPUPN03/D). Figure D-6 shows all of the host interface areas for the FQM function. MPC555 / MPC556 TPU ROM FUNCTIONS MOTOROLA USER’S MANUAL Rev. 15 October 2000 D-11 For More Information On This Product, Go to: www.freescale.com...
Page 826: D-6 Fqm Parameters
W = Primary Channel Number YY = 41 for TPU_A and 44 for TPU_B = Written By TPU = Unused Parameters Figure D-6 FQM Parameters MPC555 / MPC556 TPU ROM FUNCTIONS MOTOROLA USER’S MANUAL Rev. 15 October 2000 D-12 For More Information On This Product,...
Page 827: D.6 Universal Asynchronous Receiver/Transmitter (Uart)
Asynchronous Serial Interface TPU Function (UART), (TPUPN07/D). Figure D-7 Figure D-8 show all of the host interface areas for the UART function in transmitting and receiving modes, respectively. MPC555 / MPC556 TPU ROM FUNCTIONS MOTOROLA USER’S MANUAL Rev. 15 October 2000 D-13 For More Information On This Product, Go to: www.freescale.com...
Page 828: D-7 Uart Transmitter Parameters
W = Channel Number YY = 41 for TPU_A and 44 for TPU_B = Written By TPU = Unused Parameters Figure D-7 UART Transmitter Parameters MPC555 / MPC556 TPU ROM FUNCTIONS MOTOROLA USER’S MANUAL Rev. 15 October 2000 D-14 For More Information On This Product,...
Page 829: D-8 Uart Receiver Parameters
W = Channel Number YY = 41 for TPU_A and 44 for TPU_B = Written By TPU = Unused Parameters Figure D-8 UART Receiver Parameters MPC555 / MPC556 TPU ROM FUNCTIONS MOTOROLA USER’S MANUAL Rev. 15 October 2000 D-15 For More Information On This Product,...
Page 830: D.7 New Input Capture/Transition Counter (Nitc)
See Motorola TPU Progamming Note New Input Capture/Input Transition Counter TPU Function (NITC), (TPUPN08/D). Figure D-9 shows all of the host interface areas for the NITC function. MPC555 / MPC556 TPU ROM FUNCTIONS MOTOROLA USER’S MANUAL Rev. 15 October 2000...
Page 831: D-9 Nitc Parameters
W = Channel Number YY = 41 for TPU_A and 44 for TPU_B = Written By TPU = Unused Parameters Figure D-9 NITC Parameters MPC555 / MPC556 TPU ROM FUNCTIONS MOTOROLA USER’S MANUAL Rev. 15 October 2000 D-17 For More Information On This Product,...
Page 832: D.8 Multiphase Motor Commutation (Comm)
Multiphase Motor Commutation TPU Function (COMM), (TPUPN09/D). Figure D-10 Figure D-11 show all of the host interface areas for the COMM func- tion. MPC555 / MPC556 TPU ROM FUNCTIONS MOTOROLA USER’S MANUAL Rev. 15 October 2000 D-18 For More Information On This Product,...
Page 833: D-10 Comm Parameters (Part 1 Of 2)
W = Channel Number YY = 41 for TPU_A and 44 for TPU_B = Written By TPU = Unused Parameters Figure D-10 COMM Parameters (Part 1 of 2) MPC555 / MPC556 TPU ROM FUNCTIONS MOTOROLA USER’S MANUAL Rev. 15 October 2000 D-19 For More Information On This Product, Go to: www.freescale.com...
Page 834: D.9 Hall Effect Decode (Halld)
See Motorola TPU Progamming Note Hall Effect Decode TPU Function (HALLD), (TPUPN10/D). Figure D-12 shows all of the host interface areas for the HALLD function. MPC555 / MPC556 TPU ROM FUNCTIONS MOTOROLA USER’S MANUAL Rev. 15 October 2000 D-20 For More Information On This Product, Go to: www.freescale.com...
Page 835: D-12 Halld Parameters
= Unused Parameters NOTES: 1. Channel A Only. 2. One Channel Only (Channel B in 2-Channel Mode, Channel C in 3-Channel Mode. Figure D-12 HALLD Parameters MPC555 / MPC556 TPU ROM FUNCTIONS MOTOROLA USER’S MANUAL Rev. 15 October 2000 D-21 For More Information On This Product, Go to: www.freescale.com...
Page 836: D.10 Multichannel Pulse-Width Modulation (Mcpwm)
(MCPWM), (TPUPN05/D). Figure D-13 through Figure D-18 show the host interface areas for the MCPWM func- tion in each mode. MPC555 / MPC556 TPU ROM FUNCTIONS MOTOROLA USER’S MANUAL Rev. 15 October 2000 D-22 For More Information On This Product,...
Page 837: D-13 Mcpwm Parameters — Master Mode
W = Channel Number YY = 41 for TPU_A and 44 for TPU_B = Written By TPU = Unused Parameters Figure D-13 MCPWM Parameters — Master Mode MPC555 / MPC556 TPU ROM FUNCTIONS MOTOROLA USER’S MANUAL Rev. 15 October 2000 D-23 For More Information On This Product, Go to: www.freescale.com...
Page 838: D-14 Mcpwm Parameters — Slave Edge-Aligned Mode
W = Channel Number YY = 41 for TPU_A and 44 for TPU_B = Written By TPU = Unused Parameters Figure D-14 MCPWM Parameters — Slave Edge-Aligned Mode MPC555 / MPC556 TPU ROM FUNCTIONS MOTOROLA USER’S MANUAL Rev. 15 October 2000 D-24 For More Information On This Product, Go to: www.freescale.com...
Page 839 YY = 41 for TPU_A and 44 for TPU_B = Written By TPU = Unused Parameters Figure D-15 MCPWM Parameters — Slave Ch A Non-Inverted Center-Aligned Mode MPC555 / MPC556 TPU ROM FUNCTIONS MOTOROLA USER’S MANUAL Rev. 15 October 2000 D-25 For More Information On This Product, Go to: www.freescale.com...
Page 840 YY = 41 for TPU_A and 44 for TPU_B = Written By TPU = Unused Parameters Figure D-16 MCPWM Parameters — Slave Ch B Non-Inverted Center-Aligned Mode MPC555 / MPC556 TPU ROM FUNCTIONS MOTOROLA USER’S MANUAL Rev. 15 October 2000 D-26 For More Information On This Product, Go to: www.freescale.com...
Page 841 YY = 41 for TPU_A and 44 for TPU_B = Written By TPU = Unused Parameters Figure D-17 MCPWM Parameters — Slave Ch A Inverted Center-Aligned Mode MPC555 / MPC556 TPU ROM FUNCTIONS MOTOROLA USER’S MANUAL Rev. 15 October 2000 D-27 For More Information On This Product, Go to: www.freescale.com...
Page 842 YY = 41 for TPU_A and 44 for TPU_B = Written By TPU = Unused Parameters Figure D-18 MCPWM Parameters — Slave Ch B Non-Inverted Center-Aligned Mode MPC555 / MPC556 TPU ROM FUNCTIONS MOTOROLA USER’S MANUAL Rev. 15 October 2000 D-28 For More Information On This Product, Go to: www.freescale.com...
Page 843: D.11 Fast Quadrature Decode Tpu Function (Fqd)
Fast Quadrature Decode TPU Function (FQD), (TPUPN02/D). Figure D-19 Figure D-20 show the host interface areas for the FQD function for primary and secondary channels, respectively. MPC555 / MPC556 TPU ROM FUNCTIONS MOTOROLA USER’S MANUAL Rev. 15 October 2000 D-29 For More Information On This Product, Go to: www.freescale.com...
Page 844: D-19 Fqd Parameters — Primary Channel
W = Channel Number YY = 41 for TPU_A and 44 for TPU_B = Written By TPU = Unused Parameters Figure D-19 FQD Parameters — Primary Channel MPC555 / MPC556 TPU ROM FUNCTIONS MOTOROLA USER’S MANUAL Rev. 15 October 2000 D-30 For More Information On This Product, Go to: www.freescale.com...
Page 845: D-20 Fqd Parameters — Secondary Channel
W = Channel Number YY = 41 for TPU_A and 44 for TPU_B = Written By TPU = Unused Parameters Figure D-20 FQD Parameters — Secondary Channel MPC555 / MPC556 TPU ROM FUNCTIONS MOTOROLA USER’S MANUAL Rev. 15 October 2000 D-31 For More Information On This Product, Go to: www.freescale.com...
Page 846: D.12 Period/Pulse-Width Accumulator (Ppwa)
See Motorola TPU Progamming Note Period/Pulse-Width Accu- mulator TPU Function (PPWA), (TPUPN11/D). Figure D-21 shows the host interface areas and parameter RAM for the PPWA function. MPC555 / MPC556 TPU ROM FUNCTIONS MOTOROLA USER’S MANUAL Rev. 15 October 2000 D-32 For More Information On This Product, Go to: www.freescale.com...
Page 847: D-21 Ppwa Parameters
MAX_COUNT may be written at any time by the host CPU, but if the value written is ≤ PERIOD_COUNT, a period or pulse-width accumulation is terminated. If this happens, the number of periods over which the accumulation is done will not correspond to MAX_COUNT. Figure D-21 PPWA Parameters MPC555 / MPC556 TPU ROM FUNCTIONS MOTOROLA USER’S MANUAL Rev.
Page 848: D.13 Output Compare (Oc)
See Motorola TPU Progamming Note Output Compare TPU Function (OC), (TPUPN12/D). Figure D-22 shows the host interface areas and parameter RAM for the OC function. MPC555 / MPC556 TPU ROM FUNCTIONS MOTOROLA USER’S MANUAL Rev. 15 October 2000...
Page 849: D-22 Oc Parameters
W = Channel Number YY = 41 for TPU_A and 44 for TPU_B c= Written By TPU c= Unused Parameters Figure D-22 OC Parameters MPC555 / MPC556 TPU ROM FUNCTIONS MOTOROLA USER’S MANUAL Rev. 15 October 2000 D-35 For More Information On This Product,...
Page 850: D.14 Pulse-Width Modulation (Pwm)
See Motorola TPU Progam- ming Note Pulse-Width Modulation TPU Function (PWM), (TPUPN17/D). Figure D-23 shows the host interface areas and parameter RAM for the PWM function. MPC555 / MPC556 TPU ROM FUNCTIONS MOTOROLA USER’S MANUAL Rev. 15 October 2000 D-36 For More Information On This Product, Go to: www.freescale.com...
Page 851: D-23 Pwm Parameters
W = Channel Number YY = 41 for TPU_A and 44 for TPU_B. c= Written By TPU c= Unused Parameters Figure D-23 PWM Parameters MPC555 / MPC556 TPU ROM FUNCTIONS MOTOROLA USER’S MANUAL Rev. 15 October 2000 D-37 For More Information On This Product,...
Page 852: D.15 Discrete Input/Output (Dio)
When a pin is used as a discrete output, it is set high or low only upon request by the CPU. See Motorola TPU Progamming Note Discrete Input/Output TPU Function (DIO), (TPUPN18/D). Figure D-24 shows the host interface areas for the DIO function. MPC555 / MPC556 TPU ROM FUNCTIONS MOTOROLA USER’S MANUAL Rev. 15 October 2000 D-38 For More Information On This Product, Go to: www.freescale.com...
Page 853: D-24 Dio Parameters
W = Channel Number YY = 41 for TPU_A and 44 for TPU_B = Written By TPU = Unused Parameters Figure D-24 DIO Parameters MPC555 / MPC556 TPU ROM FUNCTIONS MOTOROLA USER’S MANUAL Rev. 15 October 2000 D-39 For More Information On This Product,...
Page 854: D.16 Synchronized Pulse-Width Modulation (Spwm)
Synchronized Pulse-Width Modulation TPU Function (SPWM), (TPUPN19/D). Figure D-25 Figure D-26 show all of the host interface areas for the SPWM func- tion. MPC555 / MPC556 TPU ROM FUNCTIONS MOTOROLA USER’S MANUAL Rev. 15 October 2000 D-40 For More Information On This Product,...
Page 855: D-25 Spwm Parameters, Part 1 Of 2
W = Channel Number YY = 41 for TPU_A and 44 for TPU_B = Written By TPU = Unused Parameters Figure D-25 SPWM Parameters, Part 1 of 2 MPC555 / MPC556 TPU ROM FUNCTIONS MOTOROLA USER’S MANUAL Rev. 15 October 2000 D-41 For More Information On This Product, Go to: www.freescale.com...
Page 856: D-26 Spwm Parameters, Part 2 Of 2
W = Channel Number YY = 41 for TPU_A and 44 for TPU_B = Written By TPU = Unused Parameters Figure D-26 SPWM Parameters, Part 2 of 2 MPC555 / MPC556 TPU ROM FUNCTIONS MOTOROLA USER’S MANUAL Rev. 15 October 2000 D-42 For More Information On This Product, Go to: www.freescale.com...
Page 857: D.17 Read / Write Timers And Pin Tpu Function (Rwtpin)
(e.g., a slave stepper motor channel). See Motorola TPU Progamming Note Using The TPU Function Library And TPU Emulation Mode, (TPUPN00/D). Figure D-27 shows all of the host interface areas for the PTA function. MPC555 / MPC556 TPU ROM FUNCTIONS MOTOROLA USER’S MANUAL Rev. 15 October 2000...
Page 858: D-27 Rwtpin Parameters
W = Channel Number YY = 41 For TPU_A 44 For TPU_B and 5C For TPU_C = Written By TPU = Unused Parameters Figure D-27 RWTPIN Parameters MPC555 / MPC556 TPU ROM FUNCTIONS MOTOROLA USER’S MANUAL Rev. 15 October 2000 D-44 For More Information On This Product, Go to: www.freescale.com...
Page 859: D.18 Id Tpu Function (Id)
This is a simple function that returns the version of the TPU ROM on the current device. Figure D-28 shows all of the host interface areas for the ID function. MPC555 / MPC556 TPU ROM FUNCTIONS MOTOROLA USER’S MANUAL Rev. 15 October 2000...
Page 860: D-28 Id Parameters
W = Channel Number YY = 41 For TPU_A 44 For TPU_B and 5C For TPU_C = Written By TPU = Unused Parameters Figure D-28 ID Parameters MPC555 / MPC556 TPU ROM FUNCTIONS MOTOROLA USER’S MANUAL Rev. 15 October 2000 D-46 For More Information On This Product, Go to: www.freescale.com...
Page 861: D.19 Serial Input/Output Port (Siop)
Da ta Out-Cha n x+1 Cloc k Out-Chan x 10-bit output only transfer, LSB first with data valid on clock falling edge Figure D-29 Two Possible SIOP Configurations MPC555 / MPC556 TPU ROM FUNCTIONS MOTOROLA USER’S MANUAL Rev. 15 October 2000...
Page 862: D.19.1 Parameters
RAM for the SIOP func- tion. The following sections describe these parameters. Note that only the clock chan- nel requires any programming — the data in and out channels are entirely under TPU microcode control. MPC555 / MPC556 TPU ROM FUNCTIONS MOTOROLA USER’S MANUAL Rev.
Page 863: D-30 Siop Parameters
W = Channel Number YY = 41 for TPU_A and 44 for TPU_B = Written By TPU = Unused Parameters Figure D-30 SIOP Parameters MPC555 / MPC556 TPU ROM FUNCTIONS MOTOROLA USER’S MANUAL Rev. 15 October 2000 D-49 For More Information On This Product,...
Page 864: D.19.1.1 Chan_Control
D.19.1.6 SIOP_DATA This parameter is the data register for all SIOP transfers. Data is shifted out of one end of SIOP_DATA and shifted in at the other end, the shift direction being determined MPC555 / MPC556 TPU ROM FUNCTIONS MOTOROLA USER’S MANUAL...
Page 865: D.19.2 Host Cpu Initialization Of The Siop Function
TPU reference manual be used along with the information given in the SIOP state timing table to perform an analysis on any pro- posed TPU application that appears to approach the performance limits of the TPU. MPC555 / MPC556 TPU ROM FUNCTIONS MOTOROLA USER’S MANUAL...
Page 866: D.19.3.1 Xfer_Size Greater Than 16
SIOP clock channel + actual SIOP service time ( = Td) and ensure that the baud rate is chosen such that HALF_PERIOD - Td is not less MPC555 / MPC556 TPU ROM FUNCTIONS MOTOROLA USER’S MANUAL...
Page 867: D-31 Siop Function Data Transition Example
1 CLO C K c h a n x D ATA IN c h a n x-1 Figure D-31 SIOP Function Data Transition Example MPC555 / MPC556 TPU ROM FUNCTIONS MOTOROLA USER’S MANUAL Rev. 15 October 2000 D-53 For More Information On This Product, Go to: www.freescale.com...
Page 868 Freescale Semiconductor, Inc. MPC555 / MPC556 TPU ROM FUNCTIONS MOTOROLA USER’S MANUAL Rev. 15 October 2000 D-54 For More Information On This Product, Go to: www.freescale.com...
Page 869: E.1 Introduction
CLOCK AND BOARD GUIDELINES E.1 INTRODUCTION The MPC555 / MPC556 built-in PLL, oscillator, and other analog and sensitive circuits, require that the board design follow special layout guidelines to ensure proper opera- tion of the chip clocks. This appendix describes how the clock supplies and external components should be connected in the board.
Page 870: E.2 Mpc555 / Mpc556 Family Power Distribution
NOTE 2: Resistor R is currently not required. Space should be left on the board to add it in the future if necessary. Figure E-1 MPC555 / MPC556 Family Power Distribution Diagram — 3 V MPC555 / MPC556 CLOCK AND BOARD GUIDELINES MOTOROLA USER’S MANUAL...
Page 871: E-2 Mpc555 / Mpc556 Family Power Distribution Diagram — 5 V And Analog
From An* (Analog Input) Sensors ~10 nF BOARD MPC555 / MPC556 Figure E-2 MPC555 / MPC556 Family Power Distribution Diagram — 5 V and Analog MPC555 / MPC556 CLOCK AND BOARD GUIDELINES MOTOROLA USER’S MANUAL Rev. 15 October 2000 For More Information On This Product,...
Page 872: E.3 Pll And Crystal Oscillator External Components
Freescale Semiconductor, Inc. E.3 PLL and Crystal Oscillator External Components E.3.1 Crystal Oscillator External Components EXTAL XTAL VSSSYN MPC555 / MPC556 BOARD NOTE: Resistor R is currently not re- quired. Figure E-3 Crystal Oscillator Circuit Table E-1 External Components Value For Different Crystals (Q1)
Page 873: E.3.2 Kapwr Filtering
Tolerance of the capacitors taken into account is ±10% E.3.2 KAPWR Filtering KAPWR pin is the MPC555 / MPC556 keep-alive power. KAPWR is used for the crys- tal oscillator circuit, and should be isolated from the noisy supplies. It is recommended that an RC filter be used on KAPWR, or bypass capacitors which are located as close as possible to the part.
Page 874: E.3.3 Pll External Components
KAP 3 V KAPWR 1 µF 100 nF VSSSYN MPC555 / MPC556 BOARD Figure E-5 Bypass Capacitors Example (Alternative) E.3.3 PLL External Components VDDSYN and VSSSYN are the PLL dedicated power supplies. These supplies must be used only for the PLL and isolated from all other noisy signals in the board.
Page 875: E.4 Clock Oscillator And Pll External Components Layout Requirements
Traces connecting capacitors, crystal, resistor should be as short as possible. There- fore, the components (crystal, resistor and capacitors) should be placed as close to the oscillator pins of the MPC555 / MPC556 as possible. MPC555 / MPC556 CLOCK AND BOARD GUIDELINES MOTOROLA USER’S MANUAL...
Page 876: E.4.2 Grounding/Guarding
E.4.2 Grounding/Guarding The traces from the oscillator pins and PLL pins of the MPC555 / MPC556 should be guarded from all other traces to reduce crosstalk. It can be provided by keeping other traces away from the oscillator circuit and placing a ground plane around the compo- nents and traces.
Page 877: F.1 Introduction
2. N is the number of clocks from external address valid till external data valid in the case of read cycle. In the case of zero wait states, N = 2. 3. Assuming BBC is parked on U-BUS. 4. Until address is valid on external pins MPC555 / MPC556 MEMORY ACCESS TIMING MOTOROLA USER’S MANUAL Rev.
Page 878 3. 8 clocks are dedicated for external access, and internal accesses are denied. 4. Assuming the external master immediately retries LEGEND Shaded areas = address phase ; Non-shaded areas = data phase MPC555 / MPC556 MEMORY ACCESS TIMING MOTOROLA USER’S MANUAL Rev.
Page 879 ELECTRICAL CHARACTERISTICS This section contains detailed information on power considerations, DC/AC electrical characteristics, and AC timing characteristics of the MPC555 / MPC556. The MPC555 / MPC556 is designed to operate at 40 MHz with nominal 3.3-V and 5.0-V power sup- plies.
Page 880: G.2 Target Failure Rate
Target failure rate of ppm pending characterization and evaluation of qualifiable silicon. G.3 Package The MPC555 / MPC556 is available in two forms, packaged and die. The package is a 272-ball PBGA, Motorola case outline 1135A-01 (See Figure 2-1 of the MPC555 Us- er’s Manual for a case drawing or contact Motorola.) For die characteristics, contact...
Page 881: G.4.3 Testing Characteristics
(MIL SPEC-883 Method 1012.1) with the cold plate temperature used for the case temperature. 7. Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per EIA/JESD51-2. MPC555 / MPC556 ELECTRICAL CHARACTERISTICS MOTOROLA USER’S MANUAL Rev.
Page 882 PBGA packages is strongly dependent on the board. temperature. If the board temperature is known, an estimate of the junction temperature in the en- vironment can be made using the following equation: MPC555 / MPC556 ELECTRICAL CHARACTERISTICS MOTOROLA USER’S MANUAL Rev.
Page 883: G.5.1 Thermal References:
G.5.1 Thermal References: Semiconductor Equipment and Materials International 805 East Middlefield Rd Mountain View, CA 94043 (415) 964-5111 MPC555 / MPC556 ELECTRICAL CHARACTERISTICS MOTOROLA USER’S MANUAL Rev. 15 October 2000 For More Information On This Product,...
Page 884: G.6 Esd Protection
2. A device will be defined as a failure if after exposure to ESD pulses the device no longer meets the device characteristic requirements. Complete DC parametric and functional testing shall be performed per appli- cable device characteristic at room temperature followed by hot temperature, unless specified otherwise in the device characteristic. MPC555 / MPC556 ELECTRICAL CHARACTERISTICS MOTOROLA USER’S MANUAL Rev.
Page 885: G.7 Dc Electrical Characteristics
Pull-up/down Inactive 5-V Input Leakage Current µA — inact5 V Pull-up/down Inactive QADC64 Input Current, Channel Off -200 -150 MPC555 / MPC556 ELECTRICAL CHARACTERISTICS MOTOROLA USER’S MANUAL Rev. 15 October 2000 For More Information On This Product, Go to: www.freescale.com...
Page 886 PQB Not Sampling — Incremental Capacitance Added During Sampling Hysteresis (Only IRQ, TPU, MIOS, GPIO, QADC — [Digital Inputs] and PORESET, HRESET, SRESET) MPC555 / MPC556 ELECTRICAL CHARACTERISTICS MOTOROLA USER’S MANUAL Rev. 15 October 2000 For More Information On This Product,...
Page 887 SLEEP, Active PLL with Clocks off DDSLP DEEP SLEEP PLL and Clocks off DDDPSLP DDI, Operating Voltage Flash Operating Voltage -0.35 V 5.50 MPC555 / MPC556 ELECTRICAL CHARACTERISTICS MOTOROLA USER’S MANUAL Rev. 15 October 2000 For More Information On This Product, Go to: www.freescale.com...
Page 888 4. Maximum leakage occurs at maximum operating temperature. Current decreases by approximately one-half for each 8 – 12°C, in the ambient temperature range of 50 – 125°C. 5. 45 pF maximum for mask sets prior to K62N MPC555 / MPC556 ELECTRICAL CHARACTERISTICS MOTOROLA USER’S MANUAL...
Page 889 $000 for values less than V . This assumes that V and V to the presence of the sample amplifier. Other channels are not affected by non-disruptive conditions. MPC555 / MPC556 ELECTRICAL CHARACTERISTICS MOTOROLA USER’S MANUAL Rev. 15 October 2000...
Page 890: G.8 Oscillator And Pll Electrical Characteristics
0.72 1.93 NOTES: 1. Values to be evaluated upon further characterization. G.9 Power Up/Down Sequencing SECTION 8 CLOCKS AND POWER CONTROL. MPC555 / MPC556 ELECTRICAL CHARACTERISTICS MOTOROLA USER’S MANUAL Rev. 15 October 2000 G-12 For More Information On This Product,...
Page 891: G.10 Flash Electrical Characteristics
2. This value is based on initial device characterization and may not be tested in production. 3. The best case (fastest) programming time of < 50 pulses is at V = 5.25 V and T = 125°C. MPC555 / MPC556 ELECTRICAL CHARACTERISTICS MOTOROLA USER’S MANUAL Rev.
Page 892: G.10.1 Flash Module Life
2. A program/erase cycle is defined as switching the bits from 1 ➝ 0 ➝ 1. 3. Reprogramming of a CMF array block prior to erase is not required. 4. Number of program/erase cycles to be adjusted pending characterization of production silicon. MPC555 / MPC556 ELECTRICAL CHARACTERISTICS MOTOROLA USER’S MANUAL...
Page 893: G.10.2 Programming And Erase Algorithm
Mode 6NL 100 ms Mode 7NL 100 ms NOTES: 1. No margin read after pulse. 2. Do margin read after each pulse. MPC555 / MPC556 ELECTRICAL CHARACTERISTICS MOTOROLA USER’S MANUAL Rev. 15 October 2000 G-15 For More Information On This Product,...
Page 894: G.11 Generic Timing
INPUTS A. Maximum Output Delay Characteristic B. Minimum Output Hold Time C. Minimum input Setup Time Characteristic D. Minimum input Hold Time Characteristic Figure G-1 CLKOUT Timing MPC555 / MPC556 ELECTRICAL CHARACTERISTICS MOTOROLA USER’S MANUAL Rev. 15 October 2000 G-16 For More Information On This Product, Go to: www.freescale.com...
Page 895 Slave mode CLKOUT to Signal Invalid 0.25TC + TCC D[0:31] CLKOUT to Signal Valid A[0:31] 0.25TC + TCC 6.25 RD/WR BURST MPC555 / MPC556 ELECTRICAL CHARACTERISTICS MOTOROLA USER’S MANUAL Rev. 15 October 2000 G-17 For More Information On This Product, Go to: www.freescale.com...
Page 896 CLKOUT to RETRY Negation (When Driven by the — Memory Controller) CLKOUT to TS, BB Signal invalid 0.25TC + 14 6.25 MPC555 / MPC556 ELECTRICAL CHARACTERISTICS MOTOROLA USER’S MANUAL Rev. 15 October 2000 G-18 For More Information On This Product,...
Page 897 -GPCM- ACS = 10, TRLX = 0 or 1 CLKOUT Falling Edge to CS Asserted 0.25TC + TCC + 1 6.25 -GPCM- ACS = 11, TRLX = 0 or 1 MPC555 / MPC556 ELECTRICAL CHARACTERISTICS MOTOROLA USER’S MANUAL Rev. 15 October 2000...
Page 898 Signal invalid -GPCM- Write Access, CSNT = ‘0’ WE[0:3]/BE[0:3] Negated to D[0:31] Signal invalid -GPCM- Write Access, TRLX = ‘0’, CSNT = ‘1’, EBDF = 0 MPC555 / MPC556 ELECTRICAL CHARACTERISTICS MOTOROLA USER’S MANUAL Rev. 15 October 2000 G-20 For More Information On This Product,...
Page 899 TRLX = ’0’, CSNT = '1’. CS Negated to A[0:31] Invalid -GPCM- Write Access, TRLX = ’0’, CSNT = '1’, ACS = 10,ACS = =’11’, EBDF = 0 MPC555 / MPC556 ELECTRICAL CHARACTERISTICS MOTOROLA USER’S MANUAL Rev. 15 October 2000...
Page 900 2. This is the maximum frequency at which ENGCLK will meet output drive and rise/fall time specifications. 3. The timing for BR ouput is relevant when the MPC555 / MPC556 is selected to work with external bus arbiter. The timing for BG output is relevant when the MPC555 / MPC556 is selected to work with internal bus arbiter.
Page 901: G-2 External Clock Timing
Freescale Semiconductor, Inc. CLKOUT Figure G-2 External Clock Timing MPC555 / MPC556 ELECTRICAL CHARACTERISTICS MOTOROLA USER’S MANUAL Rev. 15 October 2000 G-23 For More Information On This Product, Go to: www.freescale.com...
Page 902: G-3 Synchronous Output Signals Timing
Freescale Semiconductor, Inc. CLKOUT OUTPUT SIGNALS OUTPUT SIGNALS OUTPUT SIGNALS Figure G-3 Synchronous Output Signals Timing MPC555 / MPC556 ELECTRICAL CHARACTERISTICS MOTOROLA USER’S MANUAL Rev. 15 October 2000 G-24 For More Information On This Product, Go to: www.freescale.com...
Page 903: G-4 Synchronous Active Pull-Up And Open Drain Outputs Signals Timing
Freescale Semiconductor, Inc. CLKOUT TS, BB TA, BI Figure G-4 Synchronous Active Pull-Up and Open Drain Outputs Signals Timing MPC555 / MPC556 ELECTRICAL CHARACTERISTICS MOTOROLA USER’S MANUAL Rev. 15 October 2000 G-25 For More Information On This Product, Go to: www.freescale.com...
Page 904: G-5 Synchronous Input Signals Timing
Freescale Semiconductor, Inc. CLKOUT TA, BI TEA, KR, RETRY, CR BB, BG, BR Figure G-5 Synchronous Input Signals Timing MPC555 / MPC556 ELECTRICAL CHARACTERISTICS MOTOROLA USER’S MANUAL Rev. 15 October 2000 G-26 For More Information On This Product, Go to: www.freescale.com...
Page 905: G-6 Input Data Timing In Normal Case
Freescale Semiconductor, Inc. CLKOUT D[0:31] Figure G-6 Input Data Timing in Normal Case MPC555 / MPC556 ELECTRICAL CHARACTERISTICS MOTOROLA USER’S MANUAL Rev. 15 October 2000 G-27 For More Information On This Product, Go to: www.freescale.com...
Page 906: G-7 External Bus Read Timing (Gpcm Controlled — Acs = '00')
Freescale Semiconductor, Inc. CLKOUT A[0:31] WE[0:3] D[0:31] Figure G-7 External Bus Read Timing (GPCM Controlled — ACS = ‘00’) MPC555 / MPC556 ELECTRICAL CHARACTERISTICS MOTOROLA USER’S MANUAL Rev. 15 October 2000 G-28 For More Information On This Product, Go to: www.freescale.com...
Page 907: G-8 External Bus Read Timing (Gpcm Controlled — Trlx = '0' Acs = '10')
Freescale Semiconductor, Inc. CLKOUT A[0:31] D[0:31] Figure G-8 External Bus Read Timing (GPCM Controlled — TRLX = ‘0’ ACS = ‘10’) MPC555 / MPC556 ELECTRICAL CHARACTERISTICS MOTOROLA USER’S MANUAL Rev. 15 October 2000 G-29 For More Information On This Product,...
Page 908: G-9 External Bus Read Timing (Gpcm Controlled — Trlx = '0' Acs = '11')
Freescale Semiconductor, Inc. CLKOUT A[0:31] D[0:31] Figure G-9 External Bus Read Timing (GPCM Controlled — TRLX = ‘0’ ACS = ‘11’) MPC555 / MPC556 ELECTRICAL CHARACTERISTICS MOTOROLA USER’S MANUAL Rev. 15 October 2000 G-30 For More Information On This Product,...
Page 909 Freescale Semiconductor, Inc. CLKOUT A[0:31] D[0:31] Figure G-10 External Bus Read Timing (GPCM Controlled — TRLX = ‘1’, ACS = ‘10’, ACS = ‘11’) MPC555 / MPC556 ELECTRICAL CHARACTERISTICS MOTOROLA USER’S MANUAL Rev. 15 October 2000 G-31 For More Information On This Product,...
Page 910: G-11 Address Show Cycle Bus Timing
Freescale Semiconductor, Inc. CLKOUT A[0:31] Figure G-11 Address Show Cycle Bus Timing MPC555 / MPC556 ELECTRICAL CHARACTERISTICS MOTOROLA USER’S MANUAL Rev. 15 October 2000 G-32 For More Information On This Product, Go to: www.freescale.com...
Page 911: G-12 Address And Data Show Cycle Bus Timing
Freescale Semiconductor, Inc. CLKOUT A[0:31] WE[0:3] D[0:31] Figure G-12 Address and Data Show Cycle Bus Timing MPC555 / MPC556 ELECTRICAL CHARACTERISTICS MOTOROLA USER’S MANUAL Rev. 15 October 2000 G-33 For More Information On This Product, Go to: www.freescale.com...
Page 912: G-13 External Bus Write Timing (Gpcm Controlled — Trlx = '0', Csnt = '0')
Freescale Semiconductor, Inc. CLKOUT A[0:31] WE[0:3] D[0:31] Figure G-13 External Bus Write Timing (GPCM Controlled — TRLX = ‘0’, CSNT = ‘0’) MPC555 / MPC556 ELECTRICAL CHARACTERISTICS MOTOROLA USER’S MANUAL Rev. 15 October 2000 G-34 For More Information On This Product,...
Page 913: G-14 External Bus Write Timing (Gpcm Controlled — Trlx = '0', Csnt = '1')
Freescale Semiconductor, Inc. CLKOUT A[0:31] WE[0:3] D[0:31] Figure G-14 External Bus Write Timing (GPCM Controlled — TRLX = ‘0’, CSNT = ‘1’) MPC555 / MPC556 ELECTRICAL CHARACTERISTICS MOTOROLA USER’S MANUAL Rev. 15 October 2000 G-35 For More Information On This Product,...
Page 914: G-15 External Bus Write Timing (Gpcm Controlled — Trlx = '1', Csnt = '1')
Freescale Semiconductor, Inc. CLKOUT A[0:31] WE[0:3] D[0:31] Figure G-15 External Bus Write Timing (GPCM Controlled — TRLX = ‘1’, CSNT = ‘1’) MPC555 / MPC556 ELECTRICAL CHARACTERISTICS MOTOROLA USER’S MANUAL Rev. 15 October 2000 G-36 For More Information On This Product,...
Page 915: G-16 External Master Read From Internal Registers Timing
Freescale Semiconductor, Inc. CLKOUT A[0:31], TSIZ[0:1],RD/WR BURST D[0:31] RETRY Figure G-16 External Master Read from Internal Registers Timing MPC555 / MPC556 ELECTRICAL CHARACTERISTICS MOTOROLA USER’S MANUAL Rev. 15 October 2000 G-37 For More Information On This Product, Go to: www.freescale.com...
Page 916: G-17 External Master Write To Internal Registers Timing
Freescale Semiconductor, Inc. CLKOUT A[0:31], TSIZ[0:1], RD/WR BURST D[0:31] RETRY Figure G-17 External Master Write to Internal Registers Timing MPC555 / MPC556 ELECTRICAL CHARACTERISTICS MOTOROLA USER’S MANUAL Rev. 15 October 2000 G-38 For More Information On This Product, Go to: www.freescale.com...
Page 917: G.12 Interrupt Timing
The IRQ lines are synchronized internally and do not have to be asserted or negated with ref- erence to the CLKOUT. CLKOUT IRQx Figure G-18 Interrupt Detection Timing for External Level Sensitive Lines MPC555 / MPC556 ELECTRICAL CHARACTERISTICS MOTOROLA USER’S MANUAL Rev. 15 October 2000...
Page 918: G.13 Debug Port Timing
DSDI Data Hold Time — — DSCK low to DSDO Data Valid DSCK low to DSDO Invalid — — MPC555 / MPC556 ELECTRICAL CHARACTERISTICS MOTOROLA USER’S MANUAL Rev. 15 October 2000 G-40 For More Information On This Product, Go to: www.freescale.com...
Page 919: G-20 Debug Port Clock Input Timing
Freescale Semiconductor, Inc. DSCK Figure G-20 Debug Port Clock Input Timing MPC555 / MPC556 ELECTRICAL CHARACTERISTICS MOTOROLA USER’S MANUAL Rev. 15 October 2000 G-41 For More Information On This Product, Go to: www.freescale.com...
Page 920: G-21 Debug Port Timings
Freescale Semiconductor, Inc. DSCK DSDI DSDO Figure G-21 Debug Port Timings MPC555 / MPC556 ELECTRICAL CHARACTERISTICS MOTOROLA USER’S MANUAL Rev. 15 October 2000 G-42 For More Information On This Product, Go to: www.freescale.com...
Page 921: G.14 Reset Timing
2. HRESET, SRESET and PORESET have a glitch detector to ensure that spikes less than 20 ns are rejected. The internal HRESET, SRESET and PORESET will assert only if these signals are asserted for more than 100 ns. MPC555 / MPC556 ELECTRICAL CHARACTERISTICS MOTOROLA USER’S MANUAL...
Page 922: G-22 Reset Timing — Configuration From Data Bus
Freescale Semiconductor, Inc. HRESET RSTCONF D[0:31] (IN) Figure G-22 Reset Timing — Configuration from Data Bus MPC555 / MPC556 ELECTRICAL CHARACTERISTICS MOTOROLA USER’S MANUAL Rev. 15 October 2000 G-44 For More Information On This Product, Go to: www.freescale.com...
Page 923: G-23 Reset Timing — Data Bus Weak Drive During Configuration
Freescale Semiconductor, Inc. CLKOUT HRESET RSTCONF D[0:31] (OUT) (Weak) Figure G-23 Reset Timing — Data Bus Weak Drive During Configuration MPC555 / MPC556 ELECTRICAL CHARACTERISTICS MOTOROLA USER’S MANUAL Rev. 15 October 2000 G-45 For More Information On This Product, Go to: www.freescale.com...
Page 924: G-24 Reset Timing — Debug Port Configuration
Freescale Semiconductor, Inc. CLKOUT SRESET DSCK, DSDI Figure G-24 Reset Timing — Debug Port Configuration MPC555 / MPC556 ELECTRICAL CHARACTERISTICS MOTOROLA USER’S MANUAL Rev. 15 October 2000 G-46 For More Information On This Product, Go to: www.freescale.com...
Page 925: G.15 Ieee 1149.1 Electrical Characteristics
Rising Edge TCK Rising Edge to Boundary Scan — — Input Invalid NOTES: 1. JTAG timing is only tested at 10 MHz MPC555 / MPC556 ELECTRICAL CHARACTERISTICS MOTOROLA USER’S MANUAL Rev. 15 October 2000 G-47 For More Information On This Product,...
Page 926: G-25 Jtag Test Clock Input Timing
Freescale Semiconductor, Inc. Figure G-25 JTAG Test Clock Input Timing MPC555 / MPC556 ELECTRICAL CHARACTERISTICS MOTOROLA USER’S MANUAL Rev. 15 October 2000 G-48 For More Information On This Product, Go to: www.freescale.com...
Page 927: G-26 Jtag — Test Access Port Timing Diagram
Freescale Semiconductor, Inc. TMS, TDI Figure G-26 JTAG — Test Access Port Timing Diagram MPC555 / MPC556 ELECTRICAL CHARACTERISTICS MOTOROLA USER’S MANUAL Rev. 15 October 2000 G-49 For More Information On This Product, Go to: www.freescale.com...
Page 928: G-27 Jtag — Trst Timing Diagram
Freescale Semiconductor, Inc. TRST Figure G-27 JTAG — TRST Timing Diagram MPC555 / MPC556 ELECTRICAL CHARACTERISTICS MOTOROLA USER’S MANUAL Rev. 15 October 2000 G-50 For More Information On This Product, Go to: www.freescale.com...
Page 929: G-28 Boundary Scan (Jtag) Timing Diagram
Freescale Semiconductor, Inc. OUTPUT SIGNALS OUTPUT SIGNALS OUTPUT SIGNALS Figure G-28 Boundary Scan (JTAG) Timing Diagram MPC555 / MPC556 ELECTRICAL CHARACTERISTICS MOTOROLA USER’S MANUAL Rev. 15 October 2000 G-51 For More Information On This Product, Go to: www.freescale.com...
Page 930: G.16 Qadc64 Electrical Characteristics
Other channels are not affected by non-disruptive conditions. 11. Exceeding limit may cause conversion error on stressed channels and on unstressed channels. Transitions within the limit do not affect device reliability or cause permanent damage. MPC555 / MPC556 ELECTRICAL CHARACTERISTICS MOTOROLA USER’S MANUAL...
Page 931: G.17 Qsmcm Electrical Characteristics
Master 17*TC 8192*TC Slave (Does Not Require Deselect) — 13*TC Data Setup Time (Inputs) Master — Slave — MPC555 / MPC556 ELECTRICAL CHARACTERISTICS MOTOROLA USER’S MANUAL Rev. 15 October 2000 G-53 For More Information On This Product, Go to: www.freescale.com...
Page 932 2. TC is defined to be the clock period of f (IMB Clock). 3. For high time, n = External SCK rise time; for low time, n = External SCK fall time. MPC555 / MPC556 ELECTRICAL CHARACTERISTICS MOTOROLA USER’S MANUAL Rev.
Page 933: G-29 Qspi Timing — Master, Cpha = 0
DATA LSB OUT PORT DATA PORT DATA OUTPUT QSPI MAST CPHA1 Figure G-30 QSPI Timing — Master, CPHA = 1 MPC555 / MPC556 ELECTRICAL CHARACTERISTICS MOTOROLA USER’S MANUAL Rev. 15 October 2000 G-55 For More Information On This Product, Go to: www.freescale.com...
Page 934: G-31 Qspi Timing — Slave, Cpha = 0
MOSI MSB IN DATA LSB IN INPUT QSPI SLV CPHA1 Figure G-32 QSPI Timing — Slave, CPHA = 1 MPC555 / MPC556 ELECTRICAL CHARACTERISTICS MOTOROLA USER’S MANUAL Rev. 15 October 2000 G-56 For More Information On This Product, Go to: www.freescale.com...
Page 935: G.18 Gpio Electrical Characteristics
G-1. With a capacitive load > 20 nF, the user must insure that the pin is always configured as an output. 4. t is defined as the IMB Clock Period. MPC555 / MPC556 ELECTRICAL CHARACTERISTICS MOTOROLA USER’S MANUAL Rev. 15 October 2000...
Page 936: G.20 Toucan Electrical Characteristics
Up to 50 pF Load, SLRC Bit of PDMCR = “1” Serial Pins — NOTES: 1. AC timing is shown is tested to the 5-V levels outlined in Table G-4. MPC555 / MPC556 ELECTRICAL CHARACTERISTICS MOTOROLA USER’S MANUAL Rev. 15 October 2000 G-58 For More Information On This Product,...
Page 937: G.21 Mios Timing Characteristics
Note 3: vs_pclk is the MIOS prescaler clock which is distributed around the MIOS to counter modules such as the MMCSM and MPWMSM. Figure G-34 MCPSM Enable to vs_pclk Pulse Timing Diagram MPC555 / MPC556 ELECTRICAL CHARACTERISTICS MOTOROLA USER’S MANUAL Rev.
Page 938: G.21.1 Mpwmsm Timing Characteristics
7. Note: the interrupt is set before the output pin is reset (Signifying the start of a new period). PWMO MPWMO output pin Figure G-35 MPWMSM Minimum Output Pulse Example Timing Diagram MPC555 / MPC556 ELECTRICAL CHARACTERISTICS MOTOROLA USER’S MANUAL Rev.
Page 939 Rising Edge Timing Diagram PWME MPWMSCR enable MPWMO output pin Figure G-37 MPWMSM Enable to MPWMO Output Pin Rising Edge Timing Diagram MPC555 / MPC556 ELECTRICAL CHARACTERISTICS MOTOROLA USER’S MANUAL Rev. 15 October 2000 G-61 For More Information On This Product,...
Page 940: G.21.2 Mmcsm Timing Characteristics
4. The exact timing from MMCSM enable to the pin being set depends on the timing of the MMCSMSCR register write and the MCPSM vs_pclk. The MMCSM enable is taken to mean the MMCSMSCR_CLS[1:0] being written to 2‘b11. MPC555 / MPC556 ELECTRICAL CHARACTERISTICS MOTOROLA USER’S MANUAL...
Page 941: G-41 Mmcsm Load Pin To Counter Bus Reload Timing Diagram
Figure G-40 MMCSM Clock Pin to Counter Bus Increment Timing Diagram PLCB MMCSM load pin Counter bus[15:0] Figure G-41 MMCSM Load Pin to Counter Bus Reload Timing Diagram MPC555 / MPC556 ELECTRICAL CHARACTERISTICS MOTOROLA USER’S MANUAL Rev. 15 October 2000 G-63 For More Information On This Product, Go to: www.freescale.com...
Page 942 Figure G-42 MMCSM Counter Bus Reload to Interrupt Flag Setting Timing Diagram MCME MMCSMSCR_CLS[1:0] Counter bus[15:0] Figure G-43 MMCSM Prescaler Clock Select to Counter Bus Increment Timing Diagram MPC555 / MPC556 ELECTRICAL CHARACTERISTICS MOTOROLA USER’S MANUAL Rev. 15 October 2000 G-64 For More Information On This Product,...
Page 943: G-44 Mdasm Minimum Input Pin Timing Diagram
3. Maximum output resolution and pulse width depends on counter (e.g., MMCSM) and MCPSM prescaler set- tings. PPER MDAI input pin is the internal IMB clock for the IMB3 bus. Figure G-44 MDASM Minimum Input Pin Timing Diagram MPC555 / MPC556 ELECTRICAL CHARACTERISTICS MOTOROLA USER’S MANUAL Rev. 15 October 2000 G-65 For More Information On This Product, Go to: www.freescale.com...
Page 944 Figure G-46 MDASM Input Pin to MDASM Interrupt Flag Timing Diagram PULW MDAO output pin Figure G-47 MDASM Minimum Output Pulse Width Timing Diagram MPC555 / MPC556 ELECTRICAL CHARACTERISTICS MOTOROLA USER’S MANUAL Rev. 15 October 2000 G-66 For More Information On This Product,...
Page 945 5AFC 5AFD Counter bus[15:0] 5AFE MDASMAR[15:0] 5AFE Figure G-49 Counter Bus to MDASM Interrupt Flag Setting Timing Diagram MPC555 / MPC556 ELECTRICAL CHARACTERISTICS MOTOROLA USER’S MANUAL Rev. 15 October 2000 G-67 For More Information On This Product, Go to: www.freescale.com...
Page 946: G.21.4 Mpiosm Timing Characteristics
2. The minimum output pulse width depends on how quickly the CPU updates the value inside the MIOPSM_DR register. The MPC555 RCPU core takes six clock cycles to access the MIOPSM_DR register, therefore the minimum output pulse will be 12 IMB clocks.
Page 947: H.1 Electrical Characteristics
7. The typical number of pulses is at V = 5.25 V and T = 25°C. 8. After characterization this value may be improved. MPC555 / MPC556FLASH ELECTRICAL CHARACTERISTICS FOR ALL J76N MASK SETS AND 0K02A AND 1K02A ONLY MOTOROLA For More Information On This Product, Go to: www.freescale.com...
Page 948 Erase, V = 5.25 V NOTES: 1. Average current is less than 30 mA when programming both modules simultaneously. MPC555 / MPC556FLASH ELECTRICAL CHARACTERISTICS FOR ALL J76N MASK SETS AND 0K02A AND 1K02A ONLY MOTOROLA For More Information On This Product, Go to: www.freescale.com...
Page 949: H.1.1 Flash Module Life
PAWs Description (Maximum) Mode Mode 7P Positive drain ramp MPC555 / MPC556FLASH ELECTRICAL CHARACTERISTICS FOR ALL J76N MASK SETS AND 0K02A AND 1K02A ONLY MOTOROLA For More Information On This Product, Go to: www.freescale.com USER’S MANUAL Rev. 15 October 2000...
Page 950 Freescale Semiconductor, Inc. MPC555 / MPC556FLASH ELECTRICAL CHARACTERISTICS FOR ALL J76N MASK SETS AND 0K02A AND 1K02A ONLY MOTOROLA For More Information On This Product, Go to: www.freescale.com USER’S MANUAL Rev. 15 October 2000...
Page 951 9-43 enable (BITSE) 14-23 single beat transfer field (BITS) 14-17 single beat read flow, 9-8 BITSE 14-23, 14-38 MPC555 / MPC556 INDEX MOTOROLA USER’S MANUAL Rev. 15 October 2000 Index-1 For More Information On This Product,...
Page 952 CHSTPE 21-55 CR1 field 3-16 CIE1 13-37 CRCERR 16-31 CIE2 13-39 CRWE 21-50 CIER 17-15, 17-19 CRWF 21-50 CIRL 17-15 MPC555 / MPC556 INDEX MOTOROLA USER’S MANUAL Rev. 15 October 2000 Index-2 For More Information On This Product, Go to: www.freescale.com...
Page 953 Exception cause register 21-53 DIV8 clock 17-7 Exception prefix 3-21 Divide by two control field (DIV2) 17-20 Exceptions 3-34 DIW0EN 21-48 classes 3-34 MPC555 / MPC556 INDEX MOTOROLA USER’S MANUAL Rev. 15 October 2000 Index-3 For More Information On This Product,...
Page 954 General-purpose registers (GPRs) 3-12 for 0/0 3-14 Global registers 13-32 for invalid compare 3-14 for invalid integer convert 3-15 for invalid square root 3-15 MPC555 / MPC556 INDEX MOTOROLA USER’S MANUAL Rev. 15 October 2000 Index-4 For More Information On This Product,...
Page 955 TLB error interrupt, LCK 20-3 3-49 LCTRL1 21-49 IMUL–IDIV 3-5 LCTRL2 21-50 Information processing time (IPT) 16-9 MPC555 / MPC556 INDEX MOTOROLA USER’S MANUAL Rev. 15 October 2000 Index-5 For More Information On This Product, Go to: www.freescale.com...
Page 956 (NF) 14-49 /slave mode select (MSTR) 14-17 errors 14-56 master flag (NF) 14-56 external Non-IEEE 1149.1-1990 operation 22-7 MPC555 / MPC556 INDEX MOTOROLA USER’S MANUAL Rev. 15 October 2000 Index-6 For More Information On This Product, Go to: www.freescale.com...
Page 957 PF1 13-41 control PF2 13-41 for TCR1 17-5 Phase buffer segment 1/2 (PSEG1/2) bit field 16-28 for TCR2 17-7 phase-lock loop, 9-7 MPC555 / MPC556 INDEX MOTOROLA USER’S MANUAL Rev. 15 October 2000 Index-7 For More Information On This Product,...
Page 958 (CPTQP) 14-24 QASR1 13-42 end queue pointer (ENDQP) 14-24 QCLK 13-21, 13-24 new queue pointer (NEWQP) 14-24 frequency 13-25 MPC555 / MPC556 INDEX MOTOROLA USER’S MANUAL Rev. 15 October 2000 Index-8 For More Information On This Product,...
Page 959 SBK 14-47, 14-53 CMPG–CMPH 21-46 Scan modes COUNTA 21-52 single-scan modes COUNTB 21-53 external trigger 13-20 DER 21-55 SCBR 14-45 MPC555 / MPC556 INDEX MOTOROLA USER’S MANUAL Rev. 15 October 2000 Index-9 For More Information On This Product, Go to: www.freescale.com...
Page 960 STOP 13-33, 16-17, 17-11 SIW1EN 21-48 Stop SIW2EN 21-48 clocks to TCRs (CLKS) 17-13 SIW3EN 21-48 enable (STOP) bit MPC555 / MPC556 INDEX MOTOROLA USER’S MANUAL Rev. 15 October 2000 Index-10 For More Information On This Product, Go to: www.freescale.com...
Page 961 22-3 address map 17-8 data output 22-3 components 17-2 mode select 22-3 FREEZE flag (TPUF) 17-14 reset 22-3 MPC555 / MPC556 INDEX MOTOROLA USER’S MANUAL Rev. 15 October 2000 Index-11 For More Information On This Product, Go to: www.freescale.com...
Page 962 Voltage interrupt enable (TCIE) 14-54 reference pins 13-5 Transmit 13-5, 13-14, 13-47 /receive status (TX/RX) 16-31 13-5, 13-14, 13-47 MPC555 / MPC556 INDEX MOTOROLA USER’S MANUAL Rev. 15 October 2000 Index-12 For More Information On This Product, Go to: www.freescale.com...
Page 963 9-30 WRTO 14-19 –X– XE bit 3-15 XER 3-17 XX bit 3-14 –Z– ZE bit 3-15 ZX bit 3-14 MPC555 / MPC556 INDEX MOTOROLA USER’S MANUAL Rev. 15 October 2000 Index-13 For More Information On This Product, Go to: www.freescale.com...
Page 964 Freescale Semiconductor, Inc. MPC555 / MPC556 INDEX MOTOROLA USER’S MANUAL Rev. 15 October 2000 Index-14 For More Information On This Product, Go to: www.freescale.com...
Page 965 Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com...
Page 966 Freescale Semiconductor, Inc. Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages.
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