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Freescale Semiconductor
Reference Manual
MSC711x Application Development
System (MSC711xADS) Reference
Manual
MSC7110, MSC7112, MSC7113, MSC7115, MSC7116, MSC7118,
MSC7119
The MSC711xADS board uses one StarCore™-based 16-bit
MSC711x processor, the MSC7116, along with the
PowerQUICC II ™ MPC8272 as the host processor. The
MSC711xADS board serves as a platform for software and
hardware development in the MSC711x environment.
Developers can use on-board resources and the associated
debugger to perform a variety of tasks, such as downloading
and running code, setting breakpoints, displaying memory and
registers, and connecting proprietary hardware via the
expansion connectors. The MSC711xADS board can also
function as a demonstration system, with application software
programmed into its Flash memory.
The board works seamlessly with an evaluation copy of
CodeWarrior® Development Studio. The MSC711x family is a
high-performance, cost-effective family of DSPs based on the
StarCore SC1400 core, which offers system solutions,
flexibility with peripherals and performance, and overall system
cost savings. Devices in the MSC711x family target high-
bandwidth highly computational DSP applications and are
optimized for packet telephony applications, providing a
competitive price per channel for voice over packet systems.
Designed with attention to system requirements from the start,
the MSC711x family delivers one core architecture for digital
signal processing that spans the low to high end.
This manual is an operation guide for the MSC711xADS board.
It describes the board architecture and functionality and
provides instructions on how to use the board.
© Freescale Semiconductor, Inc., 2005, 2007. All rights reserved.
CONTENTS
1
Overview .................................................................3
1.1
How the MSC711xADS Works ..............................6
1.2
Product Documentation ...........................................6
1.3
Third-Party Documentation .................................... 7
2
Hardware Configuration and Boot .......................... 9
2.1
Board Unpacking ....................................................9
2.2
Board Installation ....................................................9
2.3
Board Configuration .............................................10
2.4
DIP-Switch and Jumper Settings ..........................10
2.5
MSC711xADS Boot .............................................18
2.6
Board Controls and Indicators ..............................20
3
Board-Level Functions ..........................................23
3.1
Reset ......................................................................23
3.2
Clocking ................................................................ 24
3.3
Power Supply ........................................................ 27
4
Memory Map/Programming Model ......................29
4.1
Memory Map .........................................................29
4.2
5
MSC711xADS Interfaces .....................................37
5.1
HDI16 Host Processor Interface ...........................37
5.2
60x Bus Buffering .................................................40
5.3
MSC711x Connection to the MPC8272 ...............40
5.4
RS-232 Ports .........................................................41
5.5
JTAG/OCE10 Test Access Port (TAP) .................42
5.6
DDR SDRAM Interface ........................................44
5.7
Ethernet .................................................................45
5.8
Synchronous DRAM (60x Bus) ............................46
5.9
Flash Memory .......................................................48
5.10
Time-Slot Interchanger (TSI).................................49
5.11
SLIC SLAC Interface ............................................49
5.12
E1/T1 Framer ........................................................50
MSC711xADSRM
Rev. 1, 6/2007
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Page 1: Table Of Contents
MSC711xADSRM Rev. 1, 6/2007 Reference Manual MSC711x Application Development System (MSC711xADS) Reference Manual MSC7110, MSC7112, MSC7113, MSC7115, MSC7116, MSC7118, MSC7119 CONTENTS The MSC711xADS board uses one StarCore™-based 16-bit MSC711x processor, the MSC7116, along with the Overview ..............3 PowerQUICC II ™ MPC8272 as the host processor. The How the MSC711xADS Works ......6... - Page 2 MSC711x Application Development System (MSC711xADS) Reference Manual, Rev. 1 Freescale Semiconductor...
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Page 3: Overview
• Packaging —Pb-free 400 MAPBGA (17 × 17 mm, 0.8 mm pitch). —Footprint-compatible with MSC7110, MSC7112, MSC7113, and MSC7115 • 100 MHz bus frequency, 200 MHz CPM frequency, and 400 MHz overall frequency. • Efficient, dual-core architecture that combines the PowerPC 603e ecore® with a separate RISC- based communications processor module. - Page 4 Overview Table 1-1. Features of the MSC711xADS Board (Continued) Feature Description • MPC8272 is the MSC711x host. The MPC8272 system bus connects to the MSC711x HDI. • Host/Slave connection through the 16-bit HDI16 port; the HDI16 interface is accessible via a PCI backplane multiplexed with PCI signals.
- Page 5 Figure 1-1. Full-Featured MSC711x Development Kit PSTN Fast Ethernet Ports to MSC711x E1/T1 RS-232 (MSC711x) alignment indicators JTAG/OCE10 MSC711x Device Parallel cPCI Port (Backplane) Connections RS-232 (MPC8272) Fast Ethernet JTAG/COP to MPC8272 MPC8272 device Power On/Off Voltage Input Fuse Figure 1-2. MSC711xADS External Connections MSC711x Application Development System (MSC711xADS) Reference Manual, Rev.
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Page 6: How The Msc711Xads Works
Overview 1.1 How the MSC711xADS Works The MSC711xADS allows the application engineer to upload software to both the MSC7116 and MPC8272 devices and run that software with emulated debugging devices (JTAG or a PC). The software application can run in a “bare bones” operation with only the MSC7116 and MPC8272 processors or with various input or output data streams, such as from the E1/T1 connection, the Ethernet connections, or the PSTN connections. -
Page 7: Third-Party Documentation
Third-Party Documentation Table 1-2. MSC711xADS Documentation (Continued) Name Description Order Number MSC711x Detailed functional description of the MSC711x memory and MSC711xRM Reference Manual peripheral configuration, operation, and register programming MPC8272 PowerQUICC II™ Describes the functional operation of the MPC82272 with an MPC8272RM Family Reference Manual emphasis on peripheral functions. - Page 8 Overview MSC711x Application Development System (MSC711xADS) Reference Manual, Rev. 1 Freescale Semiconductor...
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Page 9: Hardware Configuration And Boot
Board Unpacking Hardware Configuration and Boot This chapter provides unpacking, installation, and hardware preparation instructions for the MSC711xADS. It also describes the boot procedure and familiarizes you with the board controls and indicators for use during board operation. 2.1 Board Unpacking The procedure for unpacking the MSC711xADS board is as follows: Unpack the equipment from the shipping carton. -
Page 10: Board Configuration
Hardware Configuration and Boot Establish the appropriate external connections (for a list of external connections and their locations, see Figure 1-2 on page 5). Turn on the MSC711xADS voltage (SW9, as shown in Figure 1-2 on page 5). Note that ON is up and OFF is down. - Page 11 DIP-Switch and Jumper Settings • MPC8272 Hard Reset to MSC711x Hard Reset (JP6). See Section 2.4.13 on page 17. • PCI expansion enable/disable (JP7). See Section 2.4.14 on page 17. • Host (MPC8272) enable/disable (JP8). See Section 2.4.15 on page 18. LD14 - LD15 LD1 - LD13 SW1 SW2 SW3...
- Page 12 Hardware Configuration and Boot 2.4.1 Internal Voltage Supply Level (RP1) The level of internal (core) voltage is tuned via RP1 and is in the range of 0.8–1.5 V. You can measure voltage across JS5 with a digital voltmeter (DVM) or any other high input impedance voltage measurement device. Core voltage should be measured and tuned before the MSC711x processor is inserted into its socket.
- Page 13 DIP-Switch and Jumper Settings Table 2-2. SW5 Switch Settings Switch JTAG Chain Options EVENT4 EVENT3 EVENT2 EVENT1 EVENT0 TPSEL (JTAG mode) Emulator (OCE10) Scan HDI signal polarity Active high Active low HDI 8-bit bus width 8 bits 16 bits Figure 2-3. SW5 Factory Settings 2.4.4 JTAG Options (SW6)
- Page 14 Hardware Configuration and Boot Table 2-3. SW6 Settings Switch Type of Connection Chain select 1 Chain select 2 Force parallel port Auto detection Force connection C EEPROM connection MSC711x Parallel port Table 2-4. Chain Select Encoding JTAG Chain Options Chain Select 2 Chain Select 1 Separate OCE10 and COP MPC8272 and MSC711x in one chain...
- Page 15 DIP-Switch and Jumper Settings 2.4.6 MPC8272 Clock Mode Settings (SW8) Switch SW8 determines the clock settings for the MPC8272 processor. When a switch is in the ON position, its related signal is deasserted to 0. When the switch is in the OFF position, its related signal is asserted to 1. For details, refer to the MPC8272 PowerQUICC II™...
- Page 16 Hardware Configuration and Boot 2.4.9 H.110 Back Plane Reset (JP2) JP2 selects the connection of the MSC711x hard reset to the H.110 back plane. • When placed, the MSC711x hard reset is connected to the H.110 back plane reset. • When not placed, the MSC711x hard reset is disconnected from the H.110 back plane reset. Hard Reset Connected to Back Plane Hard Reset Disconnected from Back Plane Factory Default...
- Page 17 DIP-Switch and Jumper Settings 2.4.12 MPC8272 Hard Reset Configuration Word Source (JP5) JP5 selects the source for the Hard Reset Configuration Word (HRCW) of the MPC8272 processor. • In the Flash (1-2) position, the HRCW is sourced from the Flash memory. •...
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Page 18: Msc711Xads Boot
Hardware Configuration and Boot Enable Disable Factory Default Figure 2-11. JP7, PCI Enable/Disable 2.4.15 Host (MPC8272) Enable/Disable (JP8) JP8 enables and disables the host (MPC8272). When enabled, the MPC8272 is connected to the MSC711x. When disabled, the MSC711x operates in stand-alone mode, regardless of the MPC8272 state. •... - Page 19 MSC711xADS Boot E[0–2] Figure 2-13. C EEPROM Pins Table 2-7. C EEPROM Pins Description E0, E1, E2 Chip enable Serial data Serial clock Write control Supply voltage Ground The I C EEPROM is compatible with the I C memory protocol, which defines a two-wire serial interface with a bidirectional data bus and serial clock.
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Page 20: Board Controls And Indicators
Hardware Configuration and Boot 2.6 Board Controls and Indicators This section acquaints you with operational features of the MSC711xADS. 2.6.1 Abort and Reset Control Table 2-8 describes the MSC711xADS abort and reset features. Table 2-8. Abort and Reset Push Button Switches Switch Name Description... -
Page 21: Led Indicators
Board Controls and Indicators 2.6.3 GND Bridges There are seven GND bridges on the MSC711xADS. These bridges assist you in taking general measurements and establishing logic-analyzer connections. CAUTION: Shortening power connection to ground may result in permanent damage to the MSC711xADS hardware. - Page 22 Hardware Configuration and Boot Table 2-10. LED Indicators (Continued) Indication Description MSC711x MII/TDM2 Green. Indicates whether the MSC711x MII/TDM port is connected to the TDM enable device/Ethernet PHY. MSC711x MII enable Green. The MSC711x MII/TDM2 port is connected to the Ethernet PHY in MII mode.
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Page 23: Board-Level Functions
Reset Board-Level Functions This chapter discusses reset, clock, and power supply. 3.1 Reset There are several reset sources on the MSC711XADS: • Power-on reset for both the MSC711x and MPC8272 processors ( PORESET • Manual hard reset for both the MSC711x and MPC8272 processors ( HRESET •... -
Page 24: Clocking
Board-Level Functions • OCE10/JTAG port. Asserting the line connected to the OCE10/JTAG port connector directly generates HRESET a hard reset for only the MSC711x processor. • Manual hard reset. Both the MPC8272 and the MSC711x processors have their own push button. In HRESET addition, you can generate a manual hard reset for the MSC711x by toggling a bit in BCSR3. - Page 25 Clocking 3.2.2 PCI Clock The PCI bus clock is derived internally from the main clock input, . The generated PCI clock is output from CLKIN1 a PCI-dedicated PLL (named DLL). That clock output feeds an on-board low-skew and fast clock distributor that distributes the PCI clock to all on-board PCI devices.
- Page 26 Board-Level Functions Core Clock MULT CLKIN (/1 to /25) (x1 to x28) ECore clock SC1400 Core DSP Extended Core AHB DIV (/2) AHB Clock Wake-up Control to Crossbar Switch, DMA, IPBus Clock M2, Boot ROM APB Clock Device Resources DDR Clock to External.
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Page 27: Power Supply
Power Supply 3.3 Power Supply The MSC711xADS uses the following voltages: • 5 V: (Command converter). • 3.3 V: (MSC711x and MPC8272 I/O and for most of the components) • 2.5 V: (SSTL components: the DDR chip and the DDR interface in the MSC711xADS). •... - Page 28 Board-Level Functions Voltage (VIO)t 3.3 V (VSSTL)t 2.5 V (VCORE)t 1.2 V Voltage Difference Must Be > 0.7V Time Figure 3-4. MSC711xADS Power Up/Power Down Sequence From a time variant viewpoint, when power is ramped up or down, the 2.5 V supply must at any instant maintain a voltage that is at least 0.7 V less than that of the 3.3 V supply.
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Page 29: Memory Map/Programming Model
Memory Map Memory Map/Programming Model This chapter presents a recommended memory map and describes the MSC711xADS registers in detail. The MPC8272 memory controller is used as a chip-select generator to access on-board (and external) memories, saving board area and reducing cost and power consumption while increasing flexibility. When a region assigned to a buffered memory is disabled via the BCSR, the local data transceivers are disabled during access to that region to prevent possible contention on data lines. -
Page 30: Board Control And Status Registers (Bcsrx)
Memory Map/Programming Model Table 3-2. Memory Map (Continued) Address Range Memory Type Port Size Memory Size 0x04500000–0x04507FFF BCSR[0–7] 32 Bits 32 KB 0x04500000 BCSR0 4 Bytes 0x04500004 BCSR1 4 Bytes 0x04500008 BCSR2 4 Bytes 0x0450000C BCSR3 4 Bytes 0x04500010 BCSR4 4 Bytes 0x04500014 BCSR5... - Page 31 Board Control and Status Registers (BCSRx) BCSR0 Board Control Status Register 0 Offset 0x0 PQETHEN PQETH PQRSEN CONFEN Bootp — GPLLED0 GPLLED1 — TYPE RESET — TYPE RESET BCSR0 is accessed at offset 0x0 from the BCSR base address. BCSR0 gets its defaults at power-on reset. Table 4-1.
- Page 32 Memory Map/Programming Model BCSR1 Board Control Status Register 1 Offset 0x4 BVER0 BVER1 PCIEN PCIM66E PCIINTA PCIINTB PCIINTCPCIINTD TYPE RESET TYPE RESET BCSR1 can be read at any time, and it gets its defaults at power-on reset. Table 4-2. BCSR1 Bit Descriptions Reset Value Description Settings...
- Page 33 Board Control and Status Registers (BCSRx) BCSR2 Board Control Status Register 2 Offset 0x8 H8B DBREQ BM0 SWTE HDSPOL HDDS PQDMA — TYPE RESET — TYPE RESET BCSR2 is a read-only status register. It can be read at any time. Table 4-3.
- Page 34 Memory Map/Programming Model BCSR3 Board Control Status Register 3 Offset 0xC SLETHEN MIITDM2EN MIIEN SLUARTEN I2CEN SLI2CEN SLHreset HOSTEN — TYPE RESET TYPE RESET BCSR3 can be read or written at any time. Table 4-4. BCSR3 Bit Descriptions Reset Value Description Settings SLETHEN...
- Page 35 Board Control and Status Registers (BCSRx) BCSR4 Board Control Status Register 4 Offset 0x10 SYSEN GA0 EVENT0 EVENT1 EVENT2 EVENT3 EVENT4 — TYPE RESET TYPE RESET BCSR4 is a read-only register that can be read at any time. Table 3-3. BCRS4 Bit Descriptions Reset Value Description Function...
- Page 36 Memory Map/Programming Model BCSR[5 – 7] Board Control Status Registers 5–7 Offset 0x14 BCSR[5–7] are accessed at offset 0x14 from the BCSR base address. They are read-only registers that can be read at any time. Table 3-4. BCRS (5–7) Bit Descriptions Reset Value Description Type...
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Page 37: Msc711Xads Interfaces
HDI16 Host Processor Interface MSC711xADS Interfaces This chapter describes the various interfaces of the MSC711xADS, including the host interface (HDI16), the connection between the MSC711x and MPC8272 processors, RS-232 ports, OCE10/JTAG interface, Ethernet, DDR SDRAM, Flash memory, time-slot interchanger, SLIC SLAC interface, and E1/T1 framer. 5.1 HDI16 Host Processor Interface The host processor can be either the MPC8272 or an outside host, and it connects to the MSC711x processor through the HDI16 host interface, which is a 16-bit wide, full-duplex, double-buffered parallel port that can... - Page 38 MSC711xADS Interfaces 5.1.2 HDI16 BUS Connection to the Host Processor Header The host interface connector is a 36-pin, two-row header connector. The MSC711xADS board and the host board are connected via a 36-line flat cable. Figure 5-1 shows the connecting signals and the pinout of the connector. Table 5-1 describes the connector pins.
- Page 39 HDI16 Host Processor Interface Table 5-1. Host Interface Connector Pins Signal Name Attribute Description Digital GND. Main GND plane. Host interface bidirectional tri-stated data bus port: HD[0–15]. HD10 HD11 HD12 HD13 HD14 HD15 Digital GND. Main GND plane. Host Interface Address Line HA[0–3]. Bit 0 corresponds to the LSB of the bus.
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Page 40: Bus Buffering
MSC711xADS Interfaces Table 5-1. Host Interface Connector Pins (Continued) Signal Name Attribute Description Host Read/Write or Host Read Input. HRESET I/O, P.U MSC7116 Hard Reset. PORESET I/O, P.U Power-On-Reset. +3.3V Power Out. These lines are connected to the main 3.3 V plane of the MSC711xEVM. -
Page 41: Ports
RS-232 Ports 5.4 RS-232 Ports Two RS-232 ports on the MSC711xADS board assist with the development of user applications and provide convenient communication channels with a terminal or a host computer. One port connects to the MPC8272 via the MPC8272 SCC, and the second port connects to the MSC711x processor via the MSC711x UART. The RS-232 port for the MPC8272 is one 9-pin D-Type female connector. -
Page 42: Jtag/Oce10 Test Access Port (Tap)
MSC711xADS Interfaces • DCD (O). Data Carrier Detect. This line is always asserted by the MSC711xADS. • TX (O). Transmit data. • RX (I). Receive data. • DTR (I). Data terminal ready. Software on the MSC711xADS uses this signal to detect whether a terminal is connected to the MSC711xADS board. - Page 43 JTAG/OCE10 Test Access Port (TAP) You can connect the JTAG device to the MSC711xADS in one of two ways: • Direct to the appropriate external JTAG/OCE10 device. • Host-to-personal computer parallel port connection. 5.5.1 Direct Connection to External JTAG/OCE10 Device The JTAG header on the MSC711xADS provides a connection between the MSC711xADS board and any external compatible JTAG converter.
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Page 44: Ddr Sdram Interface
MSC711xADS Interfaces Table 5-2. JTAG/OCE10 Pins (Continued) Signal Attribute Description I/O,P.U. HRESET Signal When asserted by external hardware, this signal generates a hard reset sequence for the MSC7116. This sequence is asserted for 512 MSC7116 system clocks. Pulled Up on the EVM with a 1K resistor. -
Page 45: Ethernet
Ethernet VTT Regulator Note: RT is connected in this form to all the DDR lines. Data[31–0] RS-232 8 M × 16 = MSC711x Address [31–0] 8 M × 16 = DDR Interface 128 Mb RS-232 128 Mb BA[0–1] RS-232 RS-232 RS-232 RS-232 RS-232... -
Page 46: Synchronous Dram (60X Bus)
MSC711xADS Interfaces external filter to transport signals to the media in 100BASE-TX or 10BASE-T Ethernet operations. The magnetic used is TG110-S050 from Halo Engineering. MSC711x/ MPC8272 DM9161 RX[3–0] MII RX[3–0] RXERR MII RXERR RXEN MII RXEN RXCLK MII RXCLK RXDV MII RXDV Magnetic RX–... - Page 47 Synchronous DRAM (60x Bus) SDRAS SDCAS SDWE BANKSEL[1–2] SDA10 A[20–28] A[8–0] SDDQM[0–7] DQMB[0–7] D[0–63] DQ[0–63] SYSCLK MT48LC8M16A2-6 Figure 5-9. 60x SDRAM Connection Scheme 5.8.1 SDRAM Programming After power-up, software must initialize the SDRAM to establish its mode of operation, as follows: Issue the command.
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Page 48: Flash Memory
MSC711xADS Interfaces Table 5-3. DRAM Mode Register Programming (Continued) MPC8272 Mode SDRAM SDRAM Mode Value Description Register Line Address Linea Register Field SDA10 Opcode Reserved Burst read and burst write (copy-back data cache). Burst read and single write (write-through data cache). -
Page 49: Time-Slot Interchanger (Tsi)
Time-Slot Interchanger (TSI) The hard reset configuration word stored in the Flash memory is 32 bits wide, whereas that stored in the EEPROM in the BPS field (which is the boot port size) is 8 bits wide. 5.10 Time-Slot Interchanger (TSI) The MSC711xADS time-slot interchanger is from Infineon, Model PEF20451, and is a member of the SWITI family. -
Page 50: E1/T1 Framer
MSC711xADS Interfaces • Ground key detection. • DTMF detection. • Fax and modem tone (1100 Hz and 2100 Hz) detection. • DC loop current limit. • Ring generation. • Subscriber line impedance matching. • Metering signal generation. • Line circuit test. If the dual VoSLAC device is to accomplish these functions, it must receive input from the dual VoSLIC device, which senses the following parameters and scales them appropriately for the dual VoSLAC device: •... - Page 51 E1/T1 Framer TDM Bus to TSI TXTIP TXRING PM4351-NI Magnetic BADD[23–31] Framer 1:2.4 RJ45 Controls RXTIP RXRING BDAT[0–7] Figure 5-12. E1/T1 Framer Connection MSC711x Application Development System (MSC711xADS) Reference Manual, Rev. 1 Freescale Semiconductor...
- Page 52 How to Reach Us: Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products. There are no express or implied copyright licenses Home Page: granted hereunder to design or fabricate any integrated circuits or integrated circuits based on www.freescale.com the information in this document.
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