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Technical Supplement
9-16
ADDRESS DECODING
WR
RD
A10
A12
A13
A14
A15
A14
3
A15
4
A11
5
Figure 9-17: Address Decoding Circuit
U30B and U28 are used to generate the input port and output port active low
enable signals EXINEN and EXOUTEN. When address lines A15, A14, A11,
and A10 are high, and A13 is low, U28 becomes enabled. With U28 enabled,
one of the 8 outputs is set low. The output to go low is selected by pins A, B,
and C. They form a 3-bit binary number with pin C being the most significant
bit. So when address line A12 is high, WR active (low) and RD inactive (high),
a binary 5 is produced on pins A, B, and C, forcing output Y5 (EXOUTEN) low.
This enables the output port for writing. When address line A12 is high, WR
inactive and RD active, a binary 3 is produced on pins A, B, and C, forcing
output Y3 (EXINEN) low. Note that in both previous conditions, A15, A14,
A12, A11, and A10 are high and A13 is low.
The input port and the output port both share the same 1 Kbyte address space of
DC00-DFFF. When data are written to that address, the output port enable
signal EXOUTEN is activated. But when data are read from the same address,
EXINEN is activated. Because the CPU is configured to use a 16-bit bus, except
for RAM, any even address in the DC00-DFF range could be used for external
port access. In other words, reading or writing address DC00, DC02, DC04, and
so on, will all produce the same results. Due to the CPU configuration, the write
strobe WR (WRL pin), is only active for low-byte writes; therefore, both bytes
of the external output port must be written to at the same time. Because, the
upper byte of the output port cannot be written to alone, no write strobe and,
therefore, no EXOUTEN signal will be generated.
U28
1
A
Y0
2
B
Y1
3
C
Y2
Y3
Y4
6
G1
Y5
4
G2A
Y6
5
G2B
Y7
74HC138
1
2
13
U30B
6
9
10
11
74HC10
74HC10
TP71
10K
R134
VCC
EXINEN
EXOUTEN
TO: N-20
15
AUX PCB
14
13
12
11
10
DC00-DFFF
9
7
U30A
E000-FFFF
RAMEN
12
74HC10
TP74
U30C
0000-DBFF
ROMEN
8
19
20
20 HDR
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