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9.6.1.2 Address Decoding
Figure 9-16: Address Demultiplexing Circuit
U13 and U33 are transparent latches that latch the address portion of the AD bus
data on the falling edge of ALE; the outputs are always enabled. The outputs of
U13 and U33 are always the address portion of the AD bus.
The address decoding circuit is illustrated in Figure 9-17.
The CPU has a 64 Kbyte address range of 0-FFFF. RAM, EPROM, and I/O
ports share this space. The address decoding circuit splits up this space and
output enable lines to the RAM, EPROM, and I/O ports.
U30A generates the static RAMs active low enable signal, RAMEN. When
address lines A13, A14, A15 are all high, U30A's output goes low, enabling the
RAM. This occurs for the 8K address range of E000-FFFF.
ADDRESS DEMUX
U13
AD0
2
19
D1
Q1
3
18
AD1
D2
Q2
AD2
4
17
D3
Q3
AD3
5
16
D4
Q4
6
15
AD4
D5
Q5
7
14
AD5
D6
Q6
AD6
8
13
D7
Q7
AD7
9
12
D8
Q8
ALE
11
C
1
OC
TP39
74HC573
R108
10K
U33
AD8
2
19
D1
Q1
3
18
AD9
D2
Q2
AD10
4
17
D3
Q3
AD11
5
16
D4
Q4
AD12
6
15
D5
Q5
7
14
AD13
D6
Q6
AD14
8
13
D7
Q7
AD15
9
12
D8
Q8
11
ALE
C
1
OC
TP40
74HC573
R109
10K
Technical Supplement
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
9-15
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