Supermicro X11DPT-B User Manual page 38

Super X11DPT-B User's Manual
DCPMM Population Tables based on the 2nd Gen Intel Xeon
Scalable-SP Processors
Note: Only 2nd Gen Intel Xeon Scalable-SP (82xx/62xx/52xx/4215 series) processors
support DCPMM memory.
Modes P1-DIMMF1 P1-DIMMF2 P1-DIMME1
AD DRAM1 - DRAM1
MM DRAM2 - DRAM2
AD + MM DRAM3 - DRAM3
AD DCPMM - DRAM1
MM DCPMM - DRAM1
AD + MM
DCPMM - DRAM3
AD DCPMM - DRAM1
P1-DIMMF1 P1-DIMMF2 P1-DIMME1
Modes
AD DRAM1 - DRAM1
AD*
DRAM1 - DRAM1
DRAM1
DRAM2
DRAM3
Note: DDR4 single rank x8 is not available for DCPMM Memory Mode or App-Direct Mode.
•
* 2nd socket has no DCPMM DIMM
•
Mode definitions: AD=App Direct Mode, MM=Memory Mode, AD+MM=Mixed Mode
•
For MM, general DDR4+DCPMM ratio is between 1:4 and 1:16. Excessive capacity for DCPMM can be used for AD.
•
For each individual population, rearrangements between channels are allowed as long as the resulting population is
compliant with the X11 memory population rules for the 2nd Gen Intel Xeon Scalable-SP processors.
•
For each individual population, please use the same DDR4 DIMM in all slots.
•
For each individual population, sockets are normally symmetric with exceptions for 1 DCPMM per socket and 1 DCPMM
per node case. Currently, DCPMM modules operate at 2666 MHz.
•
No mixing of DCPMM and NVMDIMMs within the same platform is allowed.
•
This DCPMM population guide targets a balanced DCPMM-to-DRAM-cache ratio in MM and MM + AD modes.
Symmetric Population within 1 CPU Socket
P1-DIMME2 P1-DIMMD1 P1-DIMMD2
- DRAM1 DCPMM
- DRAM2
DCPMM
- DRAM3 DCPMM
- DRAM1 -
- DRAM1 -
- DRAM3 -
DRAM1 DRAM1 DRAM1
Asymmetric Population within 1 CPU Socket
P1-DIMME2 P1-DIMMD1 P1-DIMMD2
- DRAM1 -
- DRAM1 -
Legend (for the two tables above)
DDR4 Type
RDIMM 3DS RDIMM LRDIMM
RDIMM -
RDIMM 3DS RDIMM LRDIMM
Legend (for the first two tables above)
DCPMM Any Capacity (Uniformly for all channels for a given configuration)
38
P1-DIMMA2 P1-DIMMA1 P1-DIMMB2 P1-DIMMB1
DCPMM DRAM1 - DRAM1
DRAM2 - DRAM2
DCPMM
DCPMM DRAM3 - DRAM3
- DRAM1 - DRAM1
- DRAM1 - DRAM1
- DRAM3 - DRAM3
DRAM1 DRAM1 DRAM1 DRAM1
P1-DIMMA2 P1-DIMMA1 P1-DIMMB2 P1-DIMMB1
DCPMM DRAM1 - DRAM1
DCPMM DRAM1 - DRAM1
Capacity
3DS LRDIMM
Refer to Validation Matrix
- (DDR4 DIMMs validated with
DCPMM) below.
-
Capacity
Channel
P1-DIMMC2 P1-DIMMC1
Config.
- DRAM1 2-1-1
- DRAM2 2-1-1
- DRAM3 2-1-1
- DCPMM 1-1-1
- DCPMM 1-1-1
1-1-1
- DCPMM
- DCPMM 2-2-1
Channel
P1-DIMMC2 P1-DIMMC1
Config.
- DRAM1 2/1-1-1
2/1-1-1
- DRAM1