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Table 15: Pin Definition of SD Card Interface
Pin Name
Pin No.
SDC2_DATA3
28
SDC2_DATA2
29
SDC2_DATA1
30
SDC2_DATA0
31
SDC2_CLK
32
SDC2_CMD
33
VDD_SDIO
34
SD_INS_DET
23
The following figure shows a reference design of SD card.
Module
VDD_SDIO
R7
NM
R1 0R
SDC2_DATA3
R2 0R
SDC2_DATA2
R3 0R
SDC2_DATA1
R4 0R
SDC2_DATA0
R5 0R
SDC2_CLK
R6 0R
SDC2_CMD
SD_INS_DET
NM
In SD card interface design, in order to ensure good communication performance with SD card, the
following design principles should be complied with:
SD_INS_DET must be connected.
The voltage range of SD card power supply VDD_3V is 2.7V~3.6V and a sufficient current up to 0.8A
EG21-G_Hardware_Design
I/O
Description
IO
SD card SDIO bus DATA3
IO
SD card SDIO bus DATA2
IO
SD card SDIO bus DATA1
IO
SD card SDIO bus DATA0
DO
SD card SDIO bus clock
IO
SD card SDIO bus command
PO
SD card SDIO bus pull up power
DI
SD card insertion detection
R8
R9
R10
NM
NM
NM
C1
D1
C2
D2 C3
D3 C4
NM
NM
NM
Figure 25: Reference Circuit of SD Card
VDD_EXT
+
C10
R11
R12
100uF
NM
470K
D4 C5
D5
C6
D6
D7
NM
NM
LTE Module Series
EG21-G Hardware Design
Comment
SDIO signal level can be
selected according to SD
card supported level,
please refer to SD 3.0
protocol for more details.
If unused, keep it open.
1.8V/2.85V configurable.
Cannot be used for SD
card power. If unused,
keep it open.
1.8V power domain.
If unused, keep it open.
SD Card Connector
VDD_3V
VDD
C9
C8
C7
100nF
33pF
10pF
CD/DAT3
DAT2
DAT1
DAT0
CLK
CMD
DETECTIVE
VSS
47 / 100
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