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Quectel Manuals
Wireless modules
EG21-G
Hardware design
Quectel EG21-G Hardware Design page 24
Lte module
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:
Reference design
(23 pages)
,
Hardware design
(55 pages)
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SDC2_
29
DATA2
SDC2_
30
DATA1
EG21-G_Hardware_Design
SD card SDIO bus
IO
DATA2
SD card SDIO bus
IO
DATA1
EG21-G Hardware Design
V
min=1.4V
OH
V
min=-0.3V
IL
V
max=0.58V
IL
V
min=1.27V
IH
V
max=2.0V
IH
3.0V signaling:
V
max=0.38V
OL
V
min=2.01V
OH
V
min=-0.3V
IL
V
max=0.76V
IL
V
min=1.72V
IH
V
max=3.34V
IH
1.8V signaling:
V
max=0.45V
OL
V
min=1.4V
OH
V
min=-0.3V
IL
V
max=0.58V
IL
V
min=1.27V
IH
V
max=2.0V
IH
3.0V signaling:
V
max=0.38V
OL
V
min=2.01V
OH
V
min=-0.3V
IL
V
max=0.76V
IL
V
min=1.72V
IH
V
max=3.34V
IH
1.8V signaling:
V
max=0.45V
OL
V
min=1.4V
OH
V
min=-0.3V
IL
V
max=0.58V
IL
V
min=1.27V
IH
V
max=2.0V
IH
3.0V signaling:
V
max=0.38V
OL
V
min=2.01V
OH
V
min=-0.3V
IL
V
max=0.76V
IL
V
min=1.72V
IH
V
max=3.34V
IH
LTE Module Series
according to SD card
supported level,
please refer to SD 3.0
protocol for more
details.
If unused, keep it
open.
SDIO signal level can
be selected
according to SD card
supported level,
please refer to SD 3.0
protocol for more
details.
If unused, keep it
open.
SDIO signal level can
be selected
according to SD card
supported level,
please refer to SD 3.0
protocol for more
details.
If unused, keep it
open.
23 / 100
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