Quectel EG21-G Hardware Design page 38

Table 8: RESET_N Pin Description
Pin Name Pin No.
RESET_N 20
The recommended circuit is similar to the PWRKEY control circuit. An open drain/collector driver or button
can be used to control the RESET_N.
150ms~460ms
Reset pulse
Figure 14: Reference Circuit of RESET_N by Using Driving Circuit
Figure 15: Reference Circuit of RESET_N by Using Button
The reset scenario is illustrated in the following figure.
EG21-G_Hardware_Design
I/O Description
DI Reset the module
4.7K
47K
S2
TVS
Close to S2
LTE Module Series
EG21-G Hardware Design
Comment
1.8V power domain
RESET_N
RESET_N
37 / 100