Table A-7: Signal Characteristics For Serial Test Signal - Tektronix B020000 User Manual

Table A–7: Signal characteristics for serial test signal (Option 2 only)
Characteristics
Standards Conformance
Serial Test Signals
EDH Insertion
Field Timing Offset Range
Field Timing Offset Resolution
Vertical Timing Offset Range
Vertical Timing Offset Resolution
SPG422 Component Digital Sync Generator User Manual
Performance requirements
75% Bars
100% Bars
Full–field Pluge
Convergence
Bowtie
Active Picture Markers
Multiburst
Pulse And Bar
Ramp
Serial Digital Interface (SDI matrix)
Serial Black
White Bar
40% Gray (B040000 and above)
± 1 field
± 8 lines
Reference information
SMPTE RP 165, SMPTE 259M
See Figures A–8, A–9, and A–10.
See Figures A–11, A–12, and A–13.
See Figures A–49 and A–50.
See Figures A–34 & A–35 (H), and A–36 & A–37
(V)
See Figures A–43, A–44, and A–45.
See Figures A–38 through A–42.
See Figures A–29 and A–30.
See Figures A–31, A–32, and A–33.
See Figures A–46, A–47, and A–48.
Matrix consists of Bit Slip and Clock Recovery Test
signal and the Equalizer signal per SMPTE RP
178.
Bit Slip stresses the recovery ability of the receiver
clock regenerator by sending a string of twenty 0s
followed by a single 1.
The Equalizer Test signal contains a maximum low
frequency content. It repeats a string of nineteen
0s followed by two 1s.
525 and 625 formats available.
See Figures A–41 and A–42.
See Figures A–51 and A–52.
Can be enabled or disabled by user.
Relative to the genlock input
Video field increments
Relative to the genlock input
Video line increments
Specifications
A–15