Silicon Laboratories Si53112 User Manual

S i 5 3 11 2 E
VAL UAT I O N
Description
The Si53112-EVB can be used to evaluate the Si53112-
A01AGM, a 12-output PCIe Gen1/2/3 buffer that can
operate in either fanout or zero delay mode.
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B U '
O A R D S E R
Features
10-inch traces to evaluate signal integrity
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DC pin controls per data sheet specification.
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Ability to measure input to output propagation

delay.
Ability to measure PCIe clock jitter.
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Ability to program features of Si53112-A01AGM

via I
Si 5 3 112 - EVB
G
S U ID E
The signal traces of the input and outputs have a
single-ended impedance of 50 ohms, and differential
impedance of 100 ohms.
The series resistance on the outputs are set to match
to this impedance design.
2
C interface.