Silicon Laboratories Si53154-EVB User Manual

Si53154 E
VALUATION
Description
The Si53154 is a four port PCIe clock buffer compliant
to the PCIe Gen1, Gen2 and Gen3 standards. The
Si53154 is a 24-pin QFN device that operates on a
3.3 V power supply and can be controlled using SMBus
signals along with hardware control input pins. The
device is spread aware and accepts a frequency spread
differential clock frequency range from 100 to 210 MHz.
The connections are described in this document.
Rev. 0.1 1/12
B
OARD
GND
DIFF3 Output Enable
DIFF1 Output Enable
DIFF2 Output Enable
DIFF0 Output Enable
Copyright © 2012 by Silicon Labs
S i 5 3 15 4 - EVB
U ' G
SER S UIDE
EVB Features
This document is intended to be used in conjunction
with the Si53154 device and data sheet for the following
tests:
 PCIe Gen1, Gen2, Gen3 compliancy
 Power consumption test
 Jitter performance
2
 Testing out I C code for signal tuning
 In-system validation where SMA connectors are
present
VDD = 3.3V
power supply
Power connectors
Differential
Clock Input
SDATA
SCLK
Si53154
SRC0
SRC1
connection for
connection for
application
application
SRC3
connection
for
application
SRC2
connection
for
application
Si53154-EVB