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each
outputs
internal
register
by
CRTC
and
timing
chart
fig.
6-11,
fig.
6-12
the
output
Validate
6-4-6
Interlace/Non
6-14
Fig.
shows
the
of
the
interlace
mode
mode
is
done
by
changing
address
raster
RA0-RA3
mode
which
is
described
this
In
circuit,
the
to
raster
address
of
(1)
the
rising
By
edge
of
the
data
D3
the
address
raster
(2)
of
IC13O
Output
Q
ICl4l
is
selected
hand
On
the
other
becomes"L"level
from
ICl4l.
The
form
of
wave
at
fig.
6-l5.
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548
signal
to
terminal
output
software.
6-8
Fig.
of
each
signal
output
and
fig.
6-13.
The
address
when
signal
Interlace
switching
interlace/non-interlace
(vertical
direction
the
write
value
from
has
CRTC
different
block
at
CRTC
chapter.
raster
address
from
which
RAA1-RAA3
has
of
I/O
system
address
is
MPU
latched
by
IC130,
in
equal
both
mode.
goes7'H"_level
when
and
outputted
from
in
of
the
non-interlace
case
and
input
A
side
of
the
raster
address
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(B)
80
resolution
mode
CRT
the
by writing
shows
the
internal
each
of
mode
in
IC47,
IC49
and
ICSO
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80
character
at
s
on
power
circui
t
swi
circuit.
tching
display
mode)
and
in
internal
register
raster
address
is
CRTC
outputted
after
relationship
to
both
no
decorder
output
then
switches
by
interlace
mode
then
IC14l.
mode,
output
the
IC14l
is
selected
after
the
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address
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registers
of
is
shown
CRTC
at
to
is
the
circuit
mode.
To
switching
the
non-interlace
of
The
CRTC.
value
in
each
conversion
modes.
INTERACE
SEL,
ICl46
make
to
input
side
of
B
of
ICl3O
Q
and
outputted
switch
is
shown
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