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Hitachi MB-6890 Service Manual page 17

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*
Enable(E)
The
Enable
signal,E,
the
bus
input/output
the
ACIA.
*
Read/Write(R/W)
The
R/W
line
is
a
is
used
control
to
input/output
data
ACIA
drivers
output
when
it
is
Low,the
writes
into
selected
a
select
to
read
only
*
chip
Select(CSO,CSl
These
three
high
the
to
address
ACIA.
and
is
Low.
CS2
*
Register
Select(RS)
The
line
is
RS
high
a
level
is
A
High
used
and
level
the
Low
a
is
used
in
conjunction
in
only
register
each
Request(TR5)
*
Interrupt
is
IRQ
TTL
compatible,open
a
that
is
used
output
Low
long
the
as
as
ropriate
enable
within
*
Clock
INputs
Separate
high
impedance
for
clocking
of
transmitted
of
l,
16
64
times
or
*
Transmit
Clock(Tx
CLK)
The
is
Tx
CLK
input
data.
The
transmitter
the
clock.
*
Receive
Clock(Rx
CLK)
The
Rx
CLK
input
is
Ø
(In
the
l
the
mode,
ally.)
The
receiver
of
the
clock.
*
Serial
Input/Output
*
Receive
Data(Rx
Data)
The
line
is
Rx
Data
which
data
is
received
clock
for
detection
a
rate
in
the
are
range
tion
is
utilized.
*
Transmit
Data(Tx
Data)
The
Tx
Data
output
peripheral.
Data
rates
synchronization
is
is
high
impedance
a
data
buffers
and
clocks
high
impedance
input
the
direction
of
data
bus
interface,
When
R/W
turned
and
are
on
a
ACIA
drivers
output
register.
Therefore,
write
only
registers
or
552)
impedance
TTL
compatible
The
ACIA
is
selected
impedance
input
to
select
the
Transmit/Receive
ControVStatusRegisters.
with
Register
Select
register
pair.
drain(no
to
interrupt
the
MPU.
of
the
interrupt
cause
the
ACIA
is
set.
TTL
compatible
and
received
the
data
rate
be
may
used
for
the
clocking
initiates
data
the
on
used
for
synchronization
clock
and
data
must
of
the
samples
data
Lines
high
impedance
TTL
a
in
serial
format.
a
of
data
is
accomplished
of
O
SOO
to
kbps
when
line'transfers
serial
in
the
of
O
range
N
utilized.
T5
TTL
compatible
input
data
and
to
from
that
is
TTL
compatible
flow
through
the
ACIA's
is
High(MPU
Read
selected
register
is
turned
off
and
are
the
R/W
signal
is
within
the
ACIA.
input
lines
used
are
when
andCS1
CSO
are
that
is
TTL
compatible.
Data
Registers
The
R/W
signal
to
select
the
read
internal_pullup),active
The
IRQ
remains
output
is
and
the
present
inputs
provided
are
data.
Clock
frequencies
selected.
transmitted
of
transition
negative
of
received
data.
be
synchronized
extern-
the
positive
transition
on
compatible
input
through
Synchronization
with
internally
when
external
synchroniza-
data
modem
to
a
or
500
to
kbps
when
external
that
enables
and
cycle),
read.
the
MTU
used
High
line
Low
app-
of
clock
other

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