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simple
a
higher
the
reset
*HALT
A
Low
the
end
without
ing
the
processor
*HALT
A
Low
end
of
loss
of
the
buses
the
processor
'k
\
Bus
Available,
The
BA
output
makes
the
imply
that
additional
Low,
an
The
BS
output
state(valid
interrup
fetch(RES,NMI,FIRQ,IRQ,SWI,SWI2,SWI3).
vector
ing
of
the
indication
device.
by
Sync
Acknowledge
synchronization
Halt/Bus
condition.
All manuals and user guides at all-guides.com
R/C
network
be
may
threshold
voltage
ensures
before
the
state
level
this
input
pin
on
instruction
of
the
present
loss
When
of
data.
halted,
buses
high
impedance.
are
is
in
the
Halt
or
level
this
input
will
on
the
instruction
present
data.
When
halted,
the
high
impedance.
are
is
in
the
Halt
Bus
Status(BA,BS)
is
indication
an
MOS
buses
of
the
MPU
the
bus
will
be
available
dead
cycle
signal,
when
decoded
with
leading
edge
MPU
|
as
BA
0
0
1
0
0
1
1
1
is
Acknowledge
th§_indicated
lower
four
address
of
which
interru
t
p
is
indicated
interrupt
on
an
is
Grant
true
when
the
used
reset
to
all
that
peripherals
Processor.
the
will
MPU
cause
remainhelted
and
the
BA
output
is
also
BS
High
Bus
Grant
state.
the
MPU
to
cause
and
remain
halted
is
driven
BA
output
is
which
also
High
BS
or
Bus
Grant
State,
internal
of
control
an
high
impedance.
This
for
than
more
will
before
the
elapse
with
representing
BA,
of
Q).
State
Definition
MPU
stare
Normal
(Running)
RESET
Acknowledge
Interrupt
or
SYNC
Acknowledge
HALT
Bus Grant
or
both
during
This
lines,can
provide
the
'
level
b
eing
served
is
whi
le
the
MPU
is
waiting
line.
the
HD6809
is
in
Halt
a
11
entire
system.This
of
out
are
running
at
to
stop
indefinitely
driven
indicat-
is
High
which
indicates
the
the
running
at
stop
indefinitelywithout
High
indicating
indicates
signal
which
signal
does
not
cycle.
when
BA
one
the
MPU
acquires
the
MPU
cycle
of
hardware
a
signal,
decod-
plus
with
user
an
and
allow
vectoring
for
external
Bus
Grant
or
goes
bus.
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