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*
HD6809P/MC6809L
Micro
Processing
MTU:
(1)
Pin
arrangement
GND------~-----V"
Non-Mukabln
lnwrum
RMIUMI
| \ ¢ " U 9 K
Pm
Immun:
Request
=~=
Bus Avlxiauiq
*
B15
'
Addrusi
(2)
The
function
of
each
*
(Vcc,Vss)
Power
ground
Two
pins
used
are
O
volts,while
Vcc
'
Address
DUS(AOA¢Al5)
*
Sixteen
pins
are
the
Adress
onto
data
transfer,
a
This
is
the
"dummy
rising
All
edge
ofQ.
c *
*
" = i l a b l e ( B A )
\.J\.L\-bJ\4l¢
LJIJJ
FXVQL
load
four
TTL
or
*
Data
Bus
(D-o/D7)
eiggt
These
pins
data
bus.
Each
loads,
and
typically
*
Read/Write(R/W)
This
indicates
signal
bus.
indicates
A
Low
is
R/W
made
high
rising
edge
of
Q.
R ‹ S ‹ t ( R E S ;
*
level
A
Low
on
will
cycle
reset
TFSEl6and FFFFl6
initial
power
on,
oscillator
is
fully
Because
the
HD6809
threshold
voltage
All manuals and user guides at all-guides.com
Unit
ll
NMI
-----
-
------
E
RQ
~"' -
'-"~~
I
B
FIRQ
-~--~~~--~-
¢-|
B5
n
BA
--
--------
B
V)
---~--------
,
___
HD6809p
IE
A2
(MPU)
m
A3
A4
A5
eu!
<
m
A.
'B
A
E
AU
'
A9"
@
AW
m
A"
\A'1EE
pin.
supply
to
to
power
is
+5.0
+/-
5%.
V
d
address
to
out
ut
use
p
When
the
Bus.
processor
it
will
t
t
ddress
ou
pu__a
access"
VMA
cycle.
or
address
bus
drivers
are
is
High.
Each
LS
TTL
loads,
and
typically
'd
nication
provi
e
commu
will
drive
pin
Schottky
one
l3OpF.
th
direction
e
that
is
the
MPU
impedance
when
is
BA
this
Schmitt
trigger
the
MPU.
The
Reset
vectors
when
Interrupt
Acknowledge
the
Reset
line
should
operational.
Reset
has
Schmitt
pin
a
higher
than
that
of
YD
1
E51 HA|_r'-._--._
..-.
H,"
__
xYAL_
_____
___
_____
__
G y m
gg]
SXTAL
_______
_____En
Icwnd
gig
___
____
_____R___t
ss
Mm-,Y
........
-.-..M.m.,,
,.,,_,,
Q
_ _ _ _ _ _ _ _ _ _ _
__
__
uu______w_
..
._
"'
'Z
"
""
" " " "
E
'
" "
nabh
ommanso-
-~--DumMemoryAmer/au.Requen
~--Dum
Memory
_
3|
Do
W
EE
Dv
D2
D3
Dua
D.
nu,
Ds
E
Ds
E!o1)
@
AIS
m
A14
AddrnuEus
n|Au
is
the
Vss
ground
part;
information
does
require
not
FFFF
R/W-
High,and
-
16,
Address
valid
are
made
high
impedance
pin
will
drive
one
9OpF.
with
the
bi-directional
system
TTL
load
four
or
of
data
transfer
the
on
writing
data
the
onto
High.
R/W
is
valid
on
input
for
than
greater
fetched
from
are
'_
'
true,(BA.BS-l).
is
be
held
until
Low
trigger
input
peripherals,
standard
Amer/au.
Requen
or
the
bus
for
BS=Low
the
on
when
Shottky
LS
TTL
data
data
bus.
the
bus
one
locations
Din
-
ur
g
clock
the
with
a
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