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4.3
Signal Description
4.3.1 PCIexpress
The PCI express x1 lane is a fast connection interface for many different system devices, such as network controllers,
I/O controllers or express card devices. The implementation of this subsystem complies with the COM Express®
Specification. Implementation information is provided in the COM Express® Design Guide. Refer to the official PICMG
documentation for additional information.
The microETXexpress®-SP supports up to 5 PCIexpress x1 Lanes. See the table below for detailed configuration:
Source 1
Intel US15W PCIe #2
-
Intel US15W PCIe #1
-
-
-
-
-
-
Note1: The PCIexpress lanes can only be used in x1 configuration. No x4 lane is possible.
Note2: PCIexpress HotPlug functionality is not supported by the US15W SCH.
30
microETXexpress®-SP / microETXexpress®-SP COM Express® Connector
Optional
-
PEX8505 Port #0
PEX8505 Uplink Port #1
PEX8505 Port #2
PEX8505 Port #3
PEX8505 Port #4
-
-
-
Standard
-
PEX8509 Port #0
PEX8509 Uplink Port #1
PEX8509 Port #2
PEX8509 Port #3
PEX8509 Port #4
PEX8509 Port #5
PEX8509 Port #6
PEX8509 Port #7
Target
COMe PCIe Lane #1
COMe PCIe Lane #0
-
Intel 82574L GBLan
PEX8112 PCIe2PCI Bridge
SIL3132 PCIe2SATA Bridge
COMe PCIe Lane #2
COMe PCIe Lane #3
COMe PCIe Lane #4
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