Direct Commands From Mcu To Reader - Texas Instruments TRF7970A Manual

TRF7970A
SLOS743L – AUGUST 2011 – REVISED MARCH 2017
Table 6-18. IRQ Status Register (0x0C) for NFC and Card Emulation Operation
BIT NAME
B7 Irq_tx
B6 Irg_srx
B5 Irq_fifo
B4 Irq_err1
B3 Irq_err2
B2 Irq_err3
B1 Irq_col
B0 Irq_noresp
(1) Displays the cause of IRQ and TX/RX status
6.13.2 Initiator
The chip is fully controlled by the MCU as in RFID reader operation. The MCU activates the chip and
writes the mode selection in the ISO Control register. The normal transmit and receive procedure (through
the FIFO) are used to communicate with the TARGET device as described in

6.14 Direct Commands from MCU to Reader

6.14.1 Command Codes
Table 6-19 summarizes the command codes.
COMMAND
CODE
0x00 Idle
0x03 Software initialization
0x04 Perform RF collision avoidance
0x05 Perform response RF collision avoidance
0x06 Perform response RF collision avoidance (n = 0)
0x0F Reset FIFO
0x10 Transmission without CRC
0x11 Transmission with CRC
0x12 Delayed transmission without CRC
0x13 Delayed transmission with CRC
0x14 End of frame and transmit next time slot
0x16 Block receiver
0x17 Enable receiver
0x18 Test internal RF (RSSI at RX input with TX off)
52 Detailed Description
FUNCTION
IRQ set due to end of TX
IRQ set due to RX start
Signals the FIFO level
CRC error
Parity error
Byte framing or EOF error
Collision error
No-response time interrupt
Table 6-19. Address and Command Word Bit Distribution
COMMAND
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DESCRIPTION
Signals that TX is in progress. The flag is set at the start of
TX but the interrupt request (IRQ = 1) is sent when TX is
finished.
Signals that RX SOF was received and RX is in progress.
The flag is set at the start of RX but the interrupt request
(IRQ = 1) is sent when RX is finished.
Signals FIFO high or low as set in the Adjustable FIFO IRQ
Levels (0x14) register
Indicates receive CRC error only if B7 (no RX CRC) of ISO
Control register is set to 0.
Indicates parity error for ISO/IEC 14443 A
Indicates framing error
Collision error for ISO/IEC 14443 A and ISO/IEC 15693
single subcarrier. Bit is set if more than 6 or 7 (as defined in
register 0x10) are detected inside 1 bit period of
ISO/IEC 14443 A 106 kbps. Collision error bit can also be
triggered by external noise.
No response within the "No-response time" defined in RX
No-response Wait Time register (0x07). Signals the MCU
that next slot command can be sent. Only for
ISO/IEC 15693.
Section
Same as Power on Reset
Does not function as expected. See the
Errata for details.
Does not function as expected. See the
Errata for details.
Does not function as expected. See the
Errata for details.
Used for ISO/IEC 15693 only
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6.10.
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