Schiller AT-102 Service Handbook page 130

DS..
DSP..
DTACK
DTR
ECGI
ECGMUX
ECGO
EF
EJCT
EKGRES
FIFOR
FLM
FPIN
FWR
HREN
HSYNC
IPL0..2
IREG
ISYS
KB..
KBBEEP
KBCLR
KBCL1
KBCL2
KBIN
KBS..
KONV
LA
LEDB
Annex
A.4
Data strobe.
Digital signal processor (on program pack).
Transfer data acknowledge. Bus signal to acknowledge transfer of data.
Outgoing serial data, turns modem ON.
ECG in - serial ECG data to the CPU sent over the optical interface.
The multiplexed ECG signal from the ECG amplifier.
ECG out - serial ECG amplifier control data from the CPU sent over the optical
interface.
Empty flag.
Eject (paper tray).
Reset signal to the ECG amplifier. This signal resets the ECG amplifier to
recenter the ECG image on the LCD.
First in first out read
Control signal for frame synchronisation of the LCD.
Input for floating point co-processor.
Flag read / write.
Output enable signal for thermal print head data (History enable).
Horizontal synchronisation (video / VGA output).
Interrupt priority level (binary encoded).
Control signal from the current detector and limiter circuit on the power supply to
regulate supply.
Interrupt system (2 kHz).
Keyboard data in.
Keyboard beep (to audio amplifier).
Keyboard clear.
Keyboard clock.
Keyboard clock.
Keyboard data in - serial data from the keyboard to the CPU.
Keyboard strobe.
Convert - this signal initiates the conversion of the incoming signal from the ECG
amplifier.
Left arm.
Battery LED.
AT-102 Service Handbook