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The MCF5206e has built in logic and up to eight chip-select pins (-CS0 to -CS7) which are used to enable external
memory and I/O devices. In addition there are two -RAS lines for ADRAM's. There are registers to specify the
address range, type of access, and the method of -TA generation for each chip-select and -RAS pin. These registers
are programmed by dBUG to map the external memory and I/O devices.
The M5206eLITE uses chip-select zero (-CS0) to enable the Flash ROM (refer to Section 3.3.). The M5206eLITE
uses -RAS1, -RAS2, -CAS0, -CAS1, -CAS2, and -CAS3 to enable the ADRAM SIMM module (not populated -
refer to Section 3.2), -CS2 for FSRAM, and -CS3 for GPIO space.
The chip select mechanism of the MCF5206e allows the memory mapping to be defined based on the memory
space desired (User/Supervisor, Program/Data spaces).
All the MCF5206e internal registers, configuration registers, parallel I/O port registers, DUART registers and
system control registers are mapped by the MBAR register at any 1M-byte boundary. It is mapped to 0x10000000
by dBUG. For a complete map of these registers refer to the MCF5206e User's Manual.
The M5206eLITE board can have up to 32M bytes of 3.3V or 5V ADRAM installed. Refer to Section 3.2 for a
discussion of RAM. The dBUG is programmed in one AM29LV800BB Flash ROM which occupies 1M byte of
the address space. The ROM Monitor uses the first 128K bytes. The following thirteen 128K byte sectors are
available for the user. Refer to section 3.3.
ADDRESS RANGE
$00000000-$003FFFFF
$10000000-$100003FF
$20000000-$20001FFF
$30000000-$300FFFFF *
$40000000-$40000FFFF
$FFE00000-$FFEFFFFF
* Installed – the level 2 cache footprint accepts Motorola's MCM69F737TQ device and any other FSRAM
with the same electrical specifications and pinout.
All the unused areas of the memory map is available to the user.
3.1.9. Reset Vector Mapping
After reset, the processor attempts to get the initial stack pointer and initial program counter values from locations
$000000-$000007 (the first eight bytes of memory space). This requires the board to have a nonvolatile memory
device in this range with proper information. However, in some systems, it is preferred to have RAM starting at
address $00000000. In the MCF5206e, the -CS0 responds to any accesses after reset until the CSMR0 is written.
Since -CS0 is connected to Flash EEPROM's, the Flash EEPROMs appear to be at address $00000000 which
provides the initial stack pointer and program counter (the first 8 bytes of the Flash ROM). The initialization
routine, however, then programs the chip-select logic and locates the Flash EEPROM's to start at $FFE00000 and
the ADRAMs to start at $00000000.
3.1.10. -TA Generation
The processor starts a bus cycle by providing the necessary information (address, R/-W, etc.) and asserting the -
TS. The processor then waits for an acknowledgment (-TA) by the addressed device before it can complete the
bus cycle. This -TA is used not only to indicate the presence of a device, it also allows devices with different
access time to communicate with the processor properly. The MCF5206e, as part of the chip-select logic, has a
built in mechanism to generate the -TA for all external devices that do not have the capability to generate the -TA
signal on their own. The Flash EEPROM's and ADRAM's can not generate the -TA. Their chip-select logic is
programmed by the ROM Monitor to generate the -TA internally after a pre-programmed number of wait states.
Freescale Semiconductor, Inc.
Table 7 - The M5206eLITE memory map
SIGNAL and DEVICE
-RAS1, -RAS2, 4M bytes of ADRAM's
Internal Module registers
Internal SRAM (8K bytes)
-CS2, External FSRAM (1M byte – 256Kx32)
-CS3, 64K bytes of GPIO
-CS0, 1M byte of Flash EEPROM (512Kx16)
For More Information On This Product,
Go to: www.freescale.com
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