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System Memory
Table 1-2 shows the M5275EVB memory map.
Table 1-2. The M5275EVB Default Memory Map
Address Range
0x0000_0000 - 0x00FF_FFFF
0x2000_0000 - 0x2000_FFFF
0x3000_0000 - 0x300F_FFFF
0xFFE0_0000 - 0xFFFF_FFFF
or
0xFFC0_0000 - 0xFFFF_FFFF
1.2.5.1
Reset Vector Mapping
Asserting the reset input signal to the processor causes a reset exception. The reset
exception has the highest priority of any exception; it provides for system initialization and
recovery from catastrophic failure. Reset also aborts any processing in progress when the
reset input is recognized. Processing cannot be recovered.
The reset exception places the processor in the supervisor mode by setting the S-bit and
disables tracing by clearing the T bit in the SR. This exception also clears the M-bit and sets
the processor's interrupt priority mask in the SR to the highest level (level 7). Next, the
VBR is initialized to zero (0x0000_0000). The control registers specifying the operation of
any memories (e.g., cache and/or RAM modules) connected directly to the processor are
disabled.
Once the processor is granted the bus, it then performs two longword read bus cycles. The
first longword at address 0 is loaded into the stack pointer and the second longword at
address 4 is loaded into the program counter. After the initial instruction is fetched from
memory, program execution begins at the address in the PC. If an access error or address
error occurs before the first instruction is executed, the processor enters the fault-on-fault
halted state.
The port size of the memory that the MCF5275 accesses at address 0x0000_0000 is
determined at reset by sampling D[20:19].
Table 1-3. D[20:19] External Boot Chip Select Configuration
1-8
Chip Select
SD_CS0
—
CS1
CS0
D[20:19]
Boot Device/Data Port Size
00
Reserved
01
External (16-bit)
10
External (8-bit)
11
Reserved
M5275EVB User's Manual
Signal and Device
16 MByte SDRAM (U7)
64 KBytes Internal SRAM
512 KByte External ASRAM (not fitted) (U1)
2 MBytes External Flash (U11)
or
4 MBytes External Flash (U12)
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