Freescale Semiconductor MCF5206eLITE User Manual page 5

2.4.22. STEP - Step Over
2.4.23. SYMBOL - Symbol Name Management
2.4.24. TRACE - Trace Into
2.4.25. UPDBUG - Update the dBUG Image
2.4.26. UPUSER - Update User Code In Flash
2.5 TRAP #15 F
2.5.1. OUT_CHAR ..................................................................................................................................... 34
2.5.2. IN_CHAR ......................................................................................................................................... 35
2.5.3. CHAR_PRESENT ............................................................................................................................ 36
2.5.4. EXIT_TO_dBUG ............................................................................................................................. 36
CHAPTER 3 3-1
3.1 THE PROCESSOR AND SUPPORT LOGIC ...................................................................................... 37
3.1.1. The Processor .................................................................................................................................. 37
3.1.2. The Reset Logic ............................................................................................................................... 37
3.1.3. The -HIZ Signal ............................................................................................................................... 37
3.1.4. The Clock Circuitry ......................................................................................................................... 38
3.1.5. Watchdog Timer (BUS MONITOR) ................................................................................................. 38
3.1.6. Interrupt Sources ............................................................................................................................. 38
3.1.7. Internal SRAM ................................................................................................................................. 38
3.1.8. The MCF5206e Registers and Memory Map .................................................................................. 38
3.1.9. Reset Vector Mapping ...................................................................................................................... 39
3.1.10 -TA Generation ................................................................................................................................ 39
3.1.11 Wait State Generator ....................................................................................................................... 40
3.2 THE ASYNCHRONOUS DRAM SIMM ............................................................................................ 40
3.3 FLASH ROM ........................................................................................................................................ 40
3.3.1. JP2 Jumper and User's Program .................................................................................................... 40
3.4 THE SERIAL COMMUNICATION CHANNELS .............................................................................. 40
3.4.1. The MCF5206e UARTs .................................................................................................................... 40
3.4.2. Motorola Bus (M-Bus) Module ........................................................................................................ 41
3.5 THE PARALLEL I/O PORT ................................................................................................................. 41
3.6 THE CONNECTORS AND THE EXPANSION BUS ......................................................................... 41
3.6.1. The Terminal Connector J9 ............................................................................................................. 41
3.6.2. The Auxiliary Serial Communication Connector P2 ....................................................................... 41
3.6.3. The M-Bus/I
3.6.4. Processor Expansion Bus J1 & J2 ................................................................................................... 42
3.6.5. The Debug Connector J3 ................................................................................................................. 45
3.6.6. The 5V Tolerant GPIO Connector J10 ............................................................................................ 46
3.6.7 The GPIO Open Collector Driver Connector J11 ........................................................................... 46
3.6.8. Asynchronous DRAM SIMM Connections CN1 .............................................................................. 47
APPENDIX A PALLV16V8 CODE - PALASM4 ...................................................................................................... 49
APPENDIX B SCHEMATICS .................................................................................................................................... 51
Freescale Semiconductor, Inc.
ST ................................................................................................................ 31
TR ............................................................................................................ 32
............................................................................................................................ 34
UNCTIONS
2
C Connector J5 ........................................................................................................... 42
For More Information On This Product,
Go to: www.freescale.com
SYMBOL .................................................................. 31
UPDBUG ..................................................................... 32
UPUSER ................................................................... 33
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