Addi-Data ADDIALOG PA 358 Technical Description page 7

Analog output board
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Figures and tables
PA 358
Figures
Fig. 3-1: Wrong handling ......................................................................................................... 3
Fig. 3-2: Correct handling........................................................................................................ 3
Fig. 5-1: Component scheme................................................................................................. 6
Fig. 5-2: Jumper location and settings at delivery................................................................... 7
Fig. 6-1: DIP switches S1......................................................................................................... 12
Fig. 6-2: types of slots ............................................................................................................ 13
Fig. 6-3: Opening the protective blister pack ........................................................................ 13
Fig. 6-4: Inserting the board................................................................................................... 14
Fig. 6-5: Securing the board at the back cover .................................................................... 14
Fig. 6-6: Installation of the ADDIREG program ....................................................................... 16
Fig. 6-7: The ADDIREG registration program........................................................................... 17
Fig. 6-8: Configuring a new board ........................................................................................ 19
Fig. 6-9: Installation of the ADDI-UNINSTALL program ............................................................. 21
Fig. 6-10: The ADDI_UNINSTALL program ................................................................................ 22
Fig. 7-1: 37-pin SUB-D male connector ................................................................................. 23
Fig. 7-2: Screw terminal board PX 901 and cable ST010....................................................... 23
Fig. 7-3: Connection of the voltage output channels ........................................................... 24
Fig. 8-1: Setup (Channel 0 and 1) ......................................................................................... 25
Fig. 8-2: Schematic diagram of the watchdog circuitry........................................................ 28
Fig. 8-3: Measuring the current.............................................................................................. 31
Fig. 8-4: Description of the task ............................................................................................. 32
Fig. 8-5: Connection principle............................................................................................... 33
Fig. 8-6: Jumper settings for channel 1 & 0 in 4-20 mA......................................................... 34
Tables
Table 5-1: Jumper settings - Channel 0................................................................................... 8
Table 5-2: Jumper settings - Watchdog .................................................................................. 9
Table 5-3: I/O mapping ......................................................................................................... 10
Table 6-1: Decoding table .................................................................................................... 12
Table 8-1: Translation table.................................................................................................... 27
Table 9-1: Type Declaration for Dos and Windows 3.1X ............................................................ 35
Table 9-2: Type Declaration for Windows 95/NT ........................................................................ 36
III

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