Syncing The Boson Using Gpio Pins Of The Serdes; Adk Gmsl Latency - FLIR ADK Getting Started

FLI R ADK
The data comes across the GMSL link as a 1280 x 513 frame, where Column 1 contains the
top 8 bits of Column 1 of the VGA sensor's first column, and Column 2 contains the bottom 8
bits of the VGA sensor's first column.
Stitching the top and bottom bits will yield the correct values for the IR16 image. The
resultant frame should be the resolution of the sensor, 640x512, plus telemetry.
P1[15:8] P1[7:0]

4.8 Syncing the Boson using GPIO pins of the SerDes

The Boson can be synchronized using the GPIO pins on the serializer and deserializer. For
the MAX9295A serializer used on the ADK, one must correctly set MFP7 pin for D12 disabled.
This includes doing a register write of 0x07 to register 0x0007 (It is originally set to 0xF7).
This correctly works with the priority established by Maxim to enable GP0 over D12.
For GMSL 1, the deserializer will need to have an input into the GPI pin with a pulse width of
>0.35us. The GPI pin on the deserializer will need to be linked to MFP7 on the serializer.
To establish sync with the Boson the Boson needs to be configured to One Shot mode and
External Sync Slave mode. Note that sync pulses must be applied before the Boson is
configured to External Sync Slave mode or the Boson will fault and subsequently restart. The
Boson looks at the rising edge of the incoming sync signal, and pulse width has a wide range
of accepted variability. For the GMSL deserializer the sync pulse must be a 1.8 V logic high
pulse. Please see the Boson External Sync App Note Document for more information on the
functionality of the sync feature with the Boson camera.

4.9 ADK GMSL Latency

The FLIR ADK has an associated latency between the time when a sync pulse is received
and when MIPI data from the Deserializer reaches the SOC. This section shows the general
latency stack up of the ADK.
Table 3: The latency stackup of the ADK GMSL option.
Data
Ext Sync Pulse
Ext Sync Pulse
P2[15:8] P2[7:0]
Data Start Data Finish
Serializer Deserializer
Deserializer Boson ROIC
The information contained herein does not contain technology as
defined by EAR,15 CFR772, is publicly available, and therefore
not subject to EAR.
Ge tt in g S ta rt ed
P3[15:8] P3[7:0]
Time
35 us (GMSL 1)
10 ns (GMSL 2)
P4[15:8] P4[7:0]
Note
The SOC on Boson
has a direct feed
through to the ROIC
for frame
acquisition start
14