Nvidia Drive Systems; Upgrading The Gmsl Serializer To Gmsl 2 - FLIR ADK Getting Started

FLI R ADK

4.1 NVIDIA Drive Systems

The FLIR ADK features a heater and a shutter that are necessary for getting the most out of
the thermal core. The heater and shutter require additional power than what is typically
provided by the GMSL connection on the NVIDIA host. FLIR provides an additional power
injector circuit if your application requires it. FLIR can also provide schematics for
implementing the additional power injection on the deserializer circuit.
Connect the FLIR ADK to a FAKRA connector on the host system with the provided Coax
cable.
FLIR provides a driver for the NVIDIA drive systems that enables the use of the FLIR ADK
with the NVIDIA stack. The FLIR driver can be downloaded here.
https://flir.box.com/s/0tnhfoai7q9dq0a4qvkl0phfpo9kl26z
Follow the directions in the README.md to install the driver and get started with video
streaming.
If the NVIDIA system is setup for GMSL 2 the ADK will have to be field upgraded to GMSL 2
for our driver to work. To field upgrade the ADK to GMSL 2 see section 4.2. If you know
before hand that your system will require GMSL 2 cameras it is possible to order the ADK
configured for GMSL 2.

4.2 Upgrading the GMSL Serializer to GMSL 2

The FLIR ADKs are by shipped in either GMSL1 or GMSL 2 mode from the. The GMSL 1
cameras have the trailing part number AA1 or AAX and GMSL 2 cameras have the trailing
part number AA2. If the camera is in GMSL 1 mode and to be integrated on a GMSL 2 system
it will be necessary to configure the Serializer on the ADK to use GMSL 2. This section
describes how to configure the serializer on the ADK for GMSL 2.
ADK Serializer Address: 0x84 (8-bit addressing)
Deserializer address is typically 0x90 (Depends on system / deserializer configuration)
1) Configure deserializer for GMSL1 mode (note: in step 4 if you're not able to read back the
register from the serializer this is because the deserializer didn't get configured for GMSL 1,
a work around to configuring the deserializer to GMSL 1 is to set the CFG pin level of CFG1
to 1. This configures the deserializer to come up in GMSL1 with HIM enabled, this matches
the Serializer default configuration.)
des: write val 0x1F to reg 0x06
2) Turn on local I2C ACK on deserializer (Faked ACK response from the serializer)
des: write val 0x80 to reg 0xB0D
The information contained herein does not contain technology as
defined by EAR,15 CFR772, is publicly available, and therefore
not subject to EAR.
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