Flir voyager ii thermal imaging camera installation guide (32 pages)
Summary of Contents for FLIR ADK
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FLI R Ge tt in g S ta rt ed Getting Started guide for the FLIR ADK with USB, GMSL, and Ethernet Connector Options FLIR Systems OEM & Emerging 6769 Hollister Avenue Goleta, CA 93117 Phone: +1.805.964.9797 www.flir.com Document Number: 102-2013-105...
2 USB – Getting Started The USB option for the ADK ships with a Boson connected by USB for video and command and control, a BNC cable for external sync input, and a Mizu-P25 connector to power the window heater.
Ethernet Bridge that allows users to interact with the FLIR ADK using the standard GenICam protocol. Figure 1: The FLIR ADK GMSL option is shown on the left with the GMSL 1 to Ethernet bridge shown on the right. The information contained herein does not contain technology as defined by EAR,15 CFR772, is publicly available, and therefore not subject to EAR.
Ge tt in g S ta rt ed 3.1 Connecting the Boson ethernet ADK to the computer 1. Connect the FAKRA cable from the FLIR ADK to the GMSL – Ethernet bridge. 2. Connect the ethernet cable to a network interface card on the host computer.
3.2.1 Robot Operating System We have an example project that uses the Ethernet ADK in the ROS framework present here. https://github.com/flir/flir_adk_ethernet Once the Boson is setup to run with Linux then follow the instructions in the Readme.md to get the Boson to work with ROS.
GMSL 1 can be field upgraded to GMSL 2. In this document we provide examples of how to collect data from the GMSL ADK as well as read and write I2C commands to the ADK. We have a driver for the Nvidia Drive system and we show an example of using the Maxim MAX9296A_CSI_EVKIT to control the ADK.
If the NVIDIA system is setup for GMSL 2 the ADK will have to be field upgraded to GMSL 2 for our driver to work. To field upgrade the ADK to GMSL 2 see section 4.2. If you know before hand that your system will require GMSL 2 cameras it is possible to order the ADK configured for GMSL 2.
1 camera in a GMSL 2 configuration you need to implement this process each time. 4.3 GMSL SerDes Data Transmission The Boson core of the ADK is wired to the Maxim Serializer as shown in Table 2. Table 2: The Boson and Maxim 9295A pin correlation.
Currently the Boson camera core of the ADK will only communicate via UART. The GMSL adapter board in the ADK has a i2C to UART FIFO transceiver that will allow you to send byte array commands to the Boson. In practice the I2C to UART buffer limits the amount of data you can send to the Boson at any one time to 128 bytes.
0x0F to reg 0x18 to device reg 0xD8 Turn Heater ON Set GPIO state register on ADK side to configure heater on write val 0x09 to reg 0x19 of device reg 0xD8 Configure heater GPIO as an OUTPUT write val 0x0F to reg 0x18 of device reg 0xD8 4.5 Sample I2C Functions for Teensy SOC...
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FLI R Ge tt in g S ta rt ed byte checkRXbuffer() byte addy = 0x6C; byte = 0x12; return i2cread(transAdd, reg); delay(50); byte checkTXbuffer() byte addy = 0x6C; byte = 0x11; return i2cread(transAdd, reg); Send I2C Command Array: byte transAdd = 0x6C;...
The Boson can be synchronized using the GPIO pins on the serializer and deserializer. For the MAX9295A serializer used on the ADK, one must correctly set MFP7 pin for D12 disabled. This includes doing a register write of 0x07 to register 0x0007 (It is originally set to 0xF7).
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Boson frame readout, image processing, and CMOS data output. The latency of the Boson core of the ADK is shown below for different image processing configurations. The latency reported here is defined as the time between when the Boson receives the external sync pulse and the time when the data transmission out of the CMOS output is complete.
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FLI R Ge tt in g S ta rt ed Figure 3: 16-bit pre-AGC CMOS Output 60 Hz Figure 4: 16-bit Pre-AGC output averager ON - 30Hz The information contained herein does not contain technology as defined by EAR,15 CFR772, is publicly available, and therefore not subject to EAR.
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FLI R Ge tt in g S ta rt ed Figure 5: 8-bit post-AGC Output with averager OFF - 60Hz Figure 6: 8-bit Post colorized Averager ON 30Hz - USB video The information contained herein does not contain technology as defined by EAR,15 CFR772, is publicly available, and therefore not subject to EAR.
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