Table 4. Cdb4228A Jumper And Switch Settings; Table 5. Transmitter Clock Divider Settings - Cirrus Logic Crystal CDB4228A Manual

JUMPER
VD Selects the supply voltage for the
CS4228A digital core.
VL Selects the supply voltage for the
CS4228A logic interface pins
RX PWR Selects the supply voltage for the
Altera PLD I/O pins.
OSC PWR Connects power to the oscillator
S1 Connects power and clocks to
the CS8414
S2 Selects control port interface
S3 Selects the CS4228A SDIN1,2,3
source in EXTRNL control mode
S4 Selects the control port data for-
mat
S5 Selects serial mode and DAP
clock directions in EXTRNL con-
trol mode.
JP2 Optional pin header select for
MCLK
Notes: *Default setting from factory
8
PURPOSE
SPDIF MCLK

Table 4. CDB4228A Jumper and Switch Settings

TX-MCLK
[1..0] Division Ratio
0
*1
2
3

Table 5. Transmitter Clock Divider Settings

POSITION
3.3V*
5V
3.3V
5V*
3.3V
5V*
ON*
OFF
ON* Power and LRCLK and SCLK are connected
OFF Power, LRCLK, and SCLK are disconnected
PP* Parallel port control enabled.
EXTRNL EXTRNL CTRL header enabled
SPDIF* CS8414 data is routed to SDIN1,2,3
DAP SDIN1,2,3 source is the DAP
Two wire* Two wire control format
SPI SPI control format
CLOSED* See external control mode section for more
OPEN information.
OSC MCLK source is onboard oscillator.
MCLK source is CS8414 receiver
MUX MCLK MCLK source is multiplexer
MCLK System MCLK
Rate
1:1
1:2
1:3
1:4
CDB4228A
FUNCTION SELECTED
128
256
384
512
DS511DB1